Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[1]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[2]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[3]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[4]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[5]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[6]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[7]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[8]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[9]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[10]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[11]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[12]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[13]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[14]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[15]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[16]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[17]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[18]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[19]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[20]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[21]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[22]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[23]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[24]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[25]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[26]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[27]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[28]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[29]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[30]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[31]	6170435	1			T25	1907		T26	290		T1	25161

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105323677

1

T25

13984

T26

7199

T1

311230

auto[1]

92130243

1

T25

47040

T26

2081

T1

493922

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

165587686

1

T25

35370

T26

8769

T1

673489

auto[1]

31866234

1

T25

25654

T26

511

T1

131663

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156309175

1

T25

30424

T26

5383

T1

636438

auto[1]

41144745

1

T25

30600

T26

3897

T1

168714

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2298226	1			T25	20		T26	116		T1	7509
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2082835	1			T25	594		T26	31		T1	10505
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	498619	1			T25	376		T26	8		T1	2087
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	497712	1			T25	13		T26	109		T1	147
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	294086	1			T25	535		T26	24		T1	2863
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	498957	1			T25	369		T26	2		T1	2050
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2295801	1			T25	9		T26	164		T1	7460
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2089623	1			T25	507		T26	40		T1	10204
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	500547	1			T25	358		T26	17		T1	2226
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	494107	1			T25	30		T26	53		T1	209
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	292910	1			T25	545		T26	16		T1	3084
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	497447	1			T25	458		T1	1978		T13	202
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2293227	1			T25	18		T26	160		T1	7451
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2093022	1			T25	550		T26	33		T1	10434
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	498591	1			T25	396		T26	14		T1	2111
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	498243	1			T25	20		T26	67		T1	204
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	293602	1			T25	599		T26	14		T1	2994
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	493750	1			T25	324		T26	2		T1	1967
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2297392	1			T25	26		T26	125		T1	7425
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2082353	1			T25	537		T26	29		T1	10529
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	503312	1			T25	400		T26	12		T1	1920
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	494076	1			T25	15		T26	99		T1	189
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	293153	1			T25	519		T26	21		T1	3091
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	500149	1			T25	410		T26	4		T1	2007
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2288813	1			T25	15		T26	109		T1	7472
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2093299	1			T25	517		T26	37		T1	10377
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	501433	1			T25	479		T26	25		T1	1923
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	495423	1			T25	21		T26	82		T1	221
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	294912	1			T25	493		T26	29		T1	3270
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	496555	1			T25	382		T26	8		T1	1898
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2300444	1			T25	17		T26	148		T1	7478
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2083908	1			T25	498		T26	54		T1	10301
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	501442	1			T25	366		T26	11		T1	2183
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	494875	1			T25	31		T26	66		T1	171
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	292411	1			T25	505		T26	9		T1	2969
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	497355	1			T25	490		T26	2		T1	2059
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2299843	1			T25	16		T26	127		T1	7367
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2084703	1			T25	546		T26	33		T1	10360
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	500401	1			T25	357		T26	7		T1	2137
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	495459	1			T25	26		T26	96		T1	201
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	294253	1			T25	568		T26	19		T1	3271
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	495776	1			T25	394		T26	8		T1	1825
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2294864	1			T25	15		T26	109		T1	7388
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2086973	1			T25	530		T26	37		T1	10400
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	500284	1			T25	387		T26	19		T1	2077
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	496672	1			T25	25		T26	93		T1	172
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	293581	1			T25	524		T26	20		T1	3134
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	498061	1			T25	426		T26	12		T1	1990
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2296425	1			T25	17		T26	143		T1	7287
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2083421	1			T25	539		T26	36		T1	10301
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	501208	1			T25	341		T26	4		T1	2068
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	495965	1			T25	22		T26	77		T1	232
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	296364	1			T25	525		T26	26		T1	3143
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	497052	1			T25	463		T26	4		T1	2130
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2300802	1			T25	30		T26	93		T1	7392
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2084161	1			T25	597		T26	33		T1	10341
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	501179	1			T25	282		T26	2		T1	2262
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	495477	1			T25	19		T26	131		T1	179
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	291183	1			T25	559		T26	23		T1	2831
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	497633	1			T25	420		T26	8		T1	2156
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2295299	1			T25	15		T26	105		T1	7354
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2088770	1			T25	526		T26	25		T1	10499
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	499631	1			T25	404		T26	6		T1	2135
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	494229	1			T25	18		T26	125		T1	183
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	294462	1			T25	622		T26	18		T1	2779
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	498044	1			T25	322		T26	11		T1	2211
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2295840	1			T25	14		T26	132		T1	7538
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2088302	1			T25	564		T26	44		T1	10223
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	499190	1			T25	282		T26	10		T1	2114
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	496527	1			T25	26		T26	83		T1	228
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	293790	1			T25	534		T26	17		T1	2894
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	496786	1			T25	487		T26	4		T1	2164
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2290093	1			T25	18		T26	43		T1	7434
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2097286	1			T25	592		T26	12		T1	10499
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	500990	1			T25	324		T26	4		T1	2110
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	492744	1			T25	24		T26	154		T1	194
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	292112	1			T25	631		T26	52		T1	2996
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	497210	1			T25	318		T26	25		T1	1928
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2285726	1			T25	20		T26	106		T1	7505
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2096244	1			T25	581		T26	20		T1	10198
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	502733	1			T25	360		T26	11		T1	1998
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	493951	1			T25	21		T26	102		T1	188
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	293942	1			T25	530		T26	43		T1	3054
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	497839	1			T25	395		T26	8		T1	2218
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2294714	1			T25	20		T26	95		T1	7423
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2088291	1			T25	496		T26	43		T1	10544
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	497261	1			T25	477		T26	2		T1	2084
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	496852	1			T25	22		T26	119		T1	204
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	295936	1			T25	483		T26	27		T1	3003
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	497381	1			T25	409		T26	4		T1	1903
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2301747	1			T25	23		T26	102		T1	7478
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2079905	1			T25	445		T26	36		T1	10469
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	501141	1			T25	525		T26	6		T1	2030
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	496469	1			T25	24		T26	107		T1	218
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	293874	1			T25	500		T26	25		T1	3189
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	497299	1			T25	390		T26	14		T1	1777
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2297037	1			T25	17		T26	50		T1	7406
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2091791	1			T25	503		T26	12		T1	10221
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	495627	1			T25	477		T26	6		T1	2008
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	493755	1			T25	25		T26	168		T1	209
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	293697	1			T25	475		T26	46		T1	3195
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	498528	1			T25	410		T26	8		T1	2122
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2279954	1			T25	8		T26	61		T1	7443
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2104195	1			T25	553		T26	24		T1	10168
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	499586	1			T25	280		T26	7		T1	2194
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	497524	1			T25	23		T26	138		T1	171
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	293694	1			T25	565		T26	46		T1	3167
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	495482	1			T25	478		T26	14		T1	2018
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2290729	1			T25	12		T26	176		T1	7460
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2093091	1			T25	461		T26	47		T1	9987
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	500962	1			T25	367		T26	6		T1	1938
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	497150	1			T25	22		T26	50		T1	270
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	294096	1			T25	587		T26	11		T1	3430
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	494407	1			T25	458		T1	2076		T13	208
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2297717	1			T25	27		T26	134		T1	7410
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2086531	1			T25	584		T26	40		T1	10194
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	498121	1			T25	413		T26	2		T1	2050
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	496837	1			T25	13		T26	86		T1	173
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	295646	1			T25	423		T26	18		T1	3267
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	495583	1			T25	447		T26	10		T1	2067
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2300101	1			T25	21		T26	92		T1	7518
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2085409	1			T25	466		T26	23		T1	10298
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	496494	1			T25	398		T26	6		T1	2126
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	497978	1			T25	28		T26	113		T1	198
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	295579	1			T25	643		T26	42		T1	2937
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	494874	1			T25	351		T26	14		T1	2084
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2293674	1			T25	21		T26	118		T1	7535
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2091939	1			T25	587		T26	43		T1	10405
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	498244	1			T25	376		T26	12		T1	2107
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	498576	1			T25	21		T26	93		T1	174
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	294448	1			T25	516		T26	24		T1	2875
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	493554	1			T25	386		T1	2065		T13	211
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2301361	1			T25	22		T26	194		T1	7467
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2084873	1			T25	650		T26	62		T1	10024
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	500454	1			T25	486		T26	18		T1	2063
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	494599	1			T25	28		T26	12		T1	241
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	294641	1			T25	394		T26	2		T1	3362
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	494507	1			T25	327		T26	2		T1	2004
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2292581	1			T25	24		T26	163		T1	7459
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2096216	1			T25	525		T26	38		T1	10509
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	498730	1			T25	449		T26	9		T1	2052
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	495465	1			T25	10		T26	63		T1	187
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	292339	1			T25	555		T26	13		T1	2955
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	495104	1			T25	344		T26	4		T1	1999
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2294447	1			T25	28		T26	189		T1	7420
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2093036	1			T25	421		T26	45		T1	10510
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	495853	1			T25	542		T26	11		T1	2140
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	497738	1			T25	9		T26	36		T1	206
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	294698	1			T25	464		T26	9		T1	3009
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	494663	1			T25	443		T1	1876		T13	224
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2296654	1			T25	18		T26	177		T1	7452
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2092595	1			T25	571		T26	50		T1	10393
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	498706	1			T25	403		T26	15		T1	1990
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	494291	1			T25	17		T26	36		T1	162
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	294478	1			T25	427		T26	12		T1	3157
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	493711	1			T25	471		T1	2007		T13	188
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2296891	1			T25	20		T26	163		T1	7417
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2088268	1			T25	540		T26	39		T1	10643
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	502893	1			T25	422		T26	23		T1	2015
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	493588	1			T25	21		T26	47		T1	191
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	293663	1			T25	516		T26	16		T1	3009
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	495132	1			T25	388		T26	2		T1	1886
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2293658	1			T25	14		T26	72		T1	7327
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2092241	1			T25	541		T26	25		T1	10430
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	501759	1			T25	424		T26	1		T1	2265
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	493806	1			T25	28		T26	151		T1	172
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	294141	1			T25	499		T26	35		T1	2952
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	494830	1			T25	401		T26	6		T1	2015
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2296322	1			T25	21		T26	123		T1	7466
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2087916	1			T25	627		T26	37		T1	10332
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	498644	1			T25	336		T26	6		T1	2036
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	497777	1			T25	23		T26	83		T1	204
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	293927	1			T25	535		T26	37		T1	2958
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	495849	1			T25	365		T26	4		T1	2165
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2309569	1			T25	16		T26	74		T1	7546
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2078325	1			T25	497		T26	23		T1	10167
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	499765	1			T25	383		T26	18		T1	2073
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	496146	1			T25	23		T26	132		T1	177
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	293425	1			T25	563		T26	31		T1	2989
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	493205	1			T25	425		T26	12		T1	2209
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2298379	1			T25	26		T26	131		T1	7437
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2087481	1			T25	521		T26	35		T1	10576
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	498119	1			T25	444		T1	2142		T13	176
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	497217	1			T25	24		T26	95		T1	174
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	294543	1			T25	506		T26	16		T1	2855
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	494696	1			T25	386		T26	13		T1	1977
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2296611	1			T25	22		T26	164		T1	7496
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2094223	1			T25	467		T26	33		T1	10393
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	501089	1			T25	367		T26	8		T1	2120
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	494500	1			T25	21		T26	69		T1	177
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	292205	1			T25	594		T26	16		T1	2927
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	491807	1			T25	436		T1	2048		T13	182

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal