Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[1]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[2]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[3]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[4]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[5]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[6]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[7]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[8]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[9]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[10]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[11]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[12]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[13]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[14]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[15]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[16]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[17]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[18]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[19]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[20]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[21]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[22]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[23]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[24]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[25]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[26]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[27]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[28]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[29]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[30]	6170435	1			T25	1907		T26	290		T1	25161
bins_for_gpio_bits[31]	6170435	1			T25	1907		T26	290		T1	25161

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105323677

1

T25

13984

T26

7199

T1

311230

auto[1]

92130243

1

T25

47040

T26

2081

T1

493922

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105315398

1

T25

13991

T26

7199

T1

311274

auto[1]

92138522

1

T25

47033

T26

2081

T1

493878

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3204740	1			T25	360		T26	232		T1	9330
bins_for_gpio_bits[0]	auto[0]	auto[1]	89555	1			T25	50		T26	1		T1	417
bins_for_gpio_bits[0]	auto[1]	auto[0]	89817	1			T25	49		T26	1		T1	413
bins_for_gpio_bits[0]	auto[1]	auto[1]	2786323	1			T25	1448		T26	56		T1	15001
bins_for_gpio_bits[1]	auto[0]	auto[0]	3200846	1			T25	344		T26	234		T1	9510
bins_for_gpio_bits[1]	auto[0]	auto[1]	89310	1			T25	53		T1	386		T13	52
bins_for_gpio_bits[1]	auto[1]	auto[0]	89609	1			T25	53		T1	385		T13	52
bins_for_gpio_bits[1]	auto[1]	auto[1]	2790670	1			T25	1457		T26	56		T1	14880
bins_for_gpio_bits[2]	auto[0]	auto[0]	3200319	1			T25	381		T26	240		T1	9340
bins_for_gpio_bits[2]	auto[0]	auto[1]	89474	1			T25	53		T26	1		T1	426
bins_for_gpio_bits[2]	auto[1]	auto[0]	89742	1			T25	53		T26	1		T1	426
bins_for_gpio_bits[2]	auto[1]	auto[1]	2790900	1			T25	1420		T26	48		T1	14969
bins_for_gpio_bits[3]	auto[0]	auto[0]	3204674	1			T25	385		T26	234		T1	9171
bins_for_gpio_bits[3]	auto[0]	auto[1]	89829	1			T25	57		T26	2		T1	365
bins_for_gpio_bits[3]	auto[1]	auto[0]	90106	1			T25	56		T26	2		T1	363
bins_for_gpio_bits[3]	auto[1]	auto[1]	2785826	1			T25	1409		T26	52		T1	15262
bins_for_gpio_bits[4]	auto[0]	auto[0]	3196147	1			T25	455		T26	214		T1	9248
bins_for_gpio_bits[4]	auto[0]	auto[1]	89281	1			T25	60		T26	2		T1	370
bins_for_gpio_bits[4]	auto[1]	auto[0]	89522	1			T25	60		T26	2		T1	368
bins_for_gpio_bits[4]	auto[1]	auto[1]	2795485	1			T25	1332		T26	72		T1	15175
bins_for_gpio_bits[5]	auto[0]	auto[0]	3206502	1			T25	354		T26	224		T1	9433
bins_for_gpio_bits[5]	auto[0]	auto[1]	89977	1			T25	60		T26	1		T1	400
bins_for_gpio_bits[5]	auto[1]	auto[0]	90259	1			T25	60		T26	1		T1	399
bins_for_gpio_bits[5]	auto[1]	auto[1]	2783697	1			T25	1433		T26	64		T1	14929
bins_for_gpio_bits[6]	auto[0]	auto[0]	3205958	1			T25	350		T26	227		T1	9313
bins_for_gpio_bits[6]	auto[0]	auto[1]	89513	1			T25	50		T26	3		T1	395
bins_for_gpio_bits[6]	auto[1]	auto[0]	89745	1			T25	49		T26	3		T1	392
bins_for_gpio_bits[6]	auto[1]	auto[1]	2785219	1			T25	1458		T26	57		T1	15061
bins_for_gpio_bits[7]	auto[0]	auto[0]	3201986	1			T25	376		T26	215		T1	9240
bins_for_gpio_bits[7]	auto[0]	auto[1]	89584	1			T25	51		T26	6		T1	399
bins_for_gpio_bits[7]	auto[1]	auto[0]	89834	1			T25	51		T26	6		T1	397
bins_for_gpio_bits[7]	auto[1]	auto[1]	2789031	1			T25	1429		T26	63		T1	15125
bins_for_gpio_bits[8]	auto[0]	auto[0]	3203520	1			T25	328		T26	222		T1	9187
bins_for_gpio_bits[8]	auto[0]	auto[1]	89860	1			T25	53		T26	2		T1	400
bins_for_gpio_bits[8]	auto[1]	auto[0]	90078	1			T25	52		T26	2		T1	400
bins_for_gpio_bits[8]	auto[1]	auto[1]	2786977	1			T25	1474		T26	64		T1	15174
bins_for_gpio_bits[9]	auto[0]	auto[0]	3207362	1			T25	280		T26	222		T1	9418
bins_for_gpio_bits[9]	auto[0]	auto[1]	89839	1			T25	51		T26	4		T1	416
bins_for_gpio_bits[9]	auto[1]	auto[0]	90096	1			T25	51		T26	4		T1	415
bins_for_gpio_bits[9]	auto[1]	auto[1]	2783138	1			T25	1525		T26	60		T1	14912
bins_for_gpio_bits[10]	auto[0]	auto[0]	3199288	1			T25	377		T26	232		T1	9286
bins_for_gpio_bits[10]	auto[0]	auto[1]	89617	1			T25	60		T26	4		T1	386
bins_for_gpio_bits[10]	auto[1]	auto[0]	89871	1			T25	60		T26	4		T1	386
bins_for_gpio_bits[10]	auto[1]	auto[1]	2791659	1			T25	1410		T26	50		T1	15103
bins_for_gpio_bits[11]	auto[0]	auto[0]	3201616	1			T25	277		T26	223		T1	9492
bins_for_gpio_bits[11]	auto[0]	auto[1]	89700	1			T25	45		T26	2		T1	388
bins_for_gpio_bits[11]	auto[1]	auto[0]	89941	1			T25	45		T26	2		T1	388
bins_for_gpio_bits[11]	auto[1]	auto[1]	2789178	1			T25	1540		T26	63		T1	14893
bins_for_gpio_bits[12]	auto[0]	auto[0]	3193863	1			T25	315		T26	192		T1	9360
bins_for_gpio_bits[12]	auto[0]	auto[1]	89709	1			T25	52		T26	9		T1	380
bins_for_gpio_bits[12]	auto[1]	auto[0]	89964	1			T25	51		T26	9		T1	378
bins_for_gpio_bits[12]	auto[1]	auto[1]	2796899	1			T25	1489		T26	80		T1	15043
bins_for_gpio_bits[13]	auto[0]	auto[0]	3192563	1			T25	353		T26	216		T1	9293
bins_for_gpio_bits[13]	auto[0]	auto[1]	89546	1			T25	48		T26	3		T1	399
bins_for_gpio_bits[13]	auto[1]	auto[0]	89847	1			T25	48		T26	3		T1	398
bins_for_gpio_bits[13]	auto[1]	auto[1]	2798479	1			T25	1458		T26	68		T1	15071
bins_for_gpio_bits[14]	auto[0]	auto[0]	3199562	1			T25	466		T26	214		T1	9303
bins_for_gpio_bits[14]	auto[0]	auto[1]	89024	1			T25	53		T26	2		T1	408
bins_for_gpio_bits[14]	auto[1]	auto[0]	89265	1			T25	53		T26	2		T1	408
bins_for_gpio_bits[14]	auto[1]	auto[1]	2792584	1			T25	1335		T26	72		T1	15042
bins_for_gpio_bits[15]	auto[0]	auto[0]	3209184	1			T25	506		T26	210		T1	9341
bins_for_gpio_bits[15]	auto[0]	auto[1]	89904	1			T25	66		T26	5		T1	387
bins_for_gpio_bits[15]	auto[1]	auto[0]	90173	1			T25	66		T26	5		T1	385
bins_for_gpio_bits[15]	auto[1]	auto[1]	2781174	1			T25	1269		T26	70		T1	15048
bins_for_gpio_bits[16]	auto[0]	auto[0]	3196427	1			T25	449		T26	221		T1	9242
bins_for_gpio_bits[16]	auto[0]	auto[1]	89739	1			T25	71		T26	3		T1	381
bins_for_gpio_bits[16]	auto[1]	auto[0]	89992	1			T25	70		T26	3		T1	381
bins_for_gpio_bits[16]	auto[1]	auto[1]	2794277	1			T25	1317		T26	63		T1	15157
bins_for_gpio_bits[17]	auto[0]	auto[0]	3186950	1			T25	263		T26	203		T1	9409
bins_for_gpio_bits[17]	auto[0]	auto[1]	89848	1			T25	48		T26	3		T1	399
bins_for_gpio_bits[17]	auto[1]	auto[0]	90114	1			T25	48		T26	3		T1	399
bins_for_gpio_bits[17]	auto[1]	auto[1]	2803523	1			T25	1548		T26	81		T1	14954
bins_for_gpio_bits[18]	auto[0]	auto[0]	3198698	1			T25	359		T26	232		T1	9297
bins_for_gpio_bits[18]	auto[0]	auto[1]	89871	1			T25	42		T1	373		T13	51
bins_for_gpio_bits[18]	auto[1]	auto[0]	90143	1			T25	42		T1	371		T13	51
bins_for_gpio_bits[18]	auto[1]	auto[1]	2791723	1			T25	1464		T26	58		T1	15120
bins_for_gpio_bits[19]	auto[0]	auto[0]	3203105	1			T25	391		T26	218		T1	9241
bins_for_gpio_bits[19]	auto[0]	auto[1]	89289	1			T25	62		T26	4		T1	393
bins_for_gpio_bits[19]	auto[1]	auto[0]	89570	1			T25	62		T26	4		T1	392
bins_for_gpio_bits[19]	auto[1]	auto[1]	2788471	1			T25	1392		T26	64		T1	15135
bins_for_gpio_bits[20]	auto[0]	auto[0]	3204610	1			T25	388		T26	206		T1	9449
bins_for_gpio_bits[20]	auto[0]	auto[1]	89715	1			T25	59		T26	5		T1	394
bins_for_gpio_bits[20]	auto[1]	auto[0]	89963	1			T25	59		T26	5		T1	393
bins_for_gpio_bits[20]	auto[1]	auto[1]	2786147	1			T25	1401		T26	74		T1	14925
bins_for_gpio_bits[21]	auto[0]	auto[0]	3200342	1			T25	348		T26	223		T1	9411
bins_for_gpio_bits[21]	auto[0]	auto[1]	89897	1			T25	70		T1	408		T13	48
bins_for_gpio_bits[21]	auto[1]	auto[0]	90152	1			T25	70		T1	405		T13	49
bins_for_gpio_bits[21]	auto[1]	auto[1]	2790044	1			T25	1419		T26	67		T1	14937
bins_for_gpio_bits[22]	auto[0]	auto[0]	3206468	1			T25	471		T26	223		T1	9375
bins_for_gpio_bits[22]	auto[0]	auto[1]	89705	1			T25	66		T26	1		T1	397
bins_for_gpio_bits[22]	auto[1]	auto[0]	89946	1			T25	65		T26	1		T1	396
bins_for_gpio_bits[22]	auto[1]	auto[1]	2784316	1			T25	1305		T26	65		T1	14993
bins_for_gpio_bits[23]	auto[0]	auto[0]	3197118	1			T25	420		T26	234		T1	9296
bins_for_gpio_bits[23]	auto[0]	auto[1]	89405	1			T25	63		T26	1		T1	402
bins_for_gpio_bits[23]	auto[1]	auto[0]	89658	1			T25	63		T26	1		T1	402
bins_for_gpio_bits[23]	auto[1]	auto[1]	2794254	1			T25	1361		T26	54		T1	15061
bins_for_gpio_bits[24]	auto[0]	auto[0]	3198413	1			T25	515		T26	236		T1	9368
bins_for_gpio_bits[24]	auto[0]	auto[1]	89367	1			T25	64		T1	401		T13	48
bins_for_gpio_bits[24]	auto[1]	auto[0]	89625	1			T25	64		T1	398		T13	48
bins_for_gpio_bits[24]	auto[1]	auto[1]	2793030	1			T25	1264		T26	54		T1	14994
bins_for_gpio_bits[25]	auto[0]	auto[0]	3199876	1			T25	379		T26	228		T1	9217
bins_for_gpio_bits[25]	auto[0]	auto[1]	89545	1			T25	59		T1	389		T13	47
bins_for_gpio_bits[25]	auto[1]	auto[0]	89775	1			T25	59		T1	387		T13	47
bins_for_gpio_bits[25]	auto[1]	auto[1]	2791239	1			T25	1410		T26	62		T1	15168
bins_for_gpio_bits[26]	auto[0]	auto[0]	3203452	1			T25	398		T26	232		T1	9235
bins_for_gpio_bits[26]	auto[0]	auto[1]	89641	1			T25	65		T26	1		T1	388
bins_for_gpio_bits[26]	auto[1]	auto[0]	89920	1			T25	65		T26	1		T1	388
bins_for_gpio_bits[26]	auto[1]	auto[1]	2787422	1			T25	1379		T26	56		T1	15150
bins_for_gpio_bits[27]	auto[0]	auto[0]	3199275	1			T25	402		T26	221		T1	9338
bins_for_gpio_bits[27]	auto[0]	auto[1]	89714	1			T25	64		T26	3		T1	426
bins_for_gpio_bits[27]	auto[1]	auto[0]	89948	1			T25	64		T26	3		T1	426
bins_for_gpio_bits[27]	auto[1]	auto[1]	2791498	1			T25	1377		T26	63		T1	14971
bins_for_gpio_bits[28]	auto[0]	auto[0]	3202959	1			T25	328		T26	210		T1	9315
bins_for_gpio_bits[28]	auto[0]	auto[1]	89491	1			T25	52		T26	2		T1	394
bins_for_gpio_bits[28]	auto[1]	auto[0]	89784	1			T25	52		T26	2		T1	391
bins_for_gpio_bits[28]	auto[1]	auto[1]	2788201	1			T25	1475		T26	76		T1	15061
bins_for_gpio_bits[29]	auto[0]	auto[0]	3215989	1			T25	368		T26	221		T1	9376
bins_for_gpio_bits[29]	auto[0]	auto[1]	89258	1			T25	54		T26	3		T1	422
bins_for_gpio_bits[29]	auto[1]	auto[0]	89491	1			T25	54		T26	3		T1	420
bins_for_gpio_bits[29]	auto[1]	auto[1]	2775697	1			T25	1431		T26	63		T1	14943
bins_for_gpio_bits[30]	auto[0]	auto[0]	3203711	1			T25	423		T26	220		T1	9367
bins_for_gpio_bits[30]	auto[0]	auto[1]	89730	1			T25	71		T26	6		T1	390
bins_for_gpio_bits[30]	auto[1]	auto[0]	90004	1			T25	71		T26	6		T1	386
bins_for_gpio_bits[30]	auto[1]	auto[1]	2786990	1			T25	1342		T26	58		T1	15018
bins_for_gpio_bits[31]	auto[0]	auto[0]	3201872	1			T25	351		T26	241		T1	9397
bins_for_gpio_bits[31]	auto[0]	auto[1]	90066	1			T25	59		T1	397		T13	46
bins_for_gpio_bits[31]	auto[1]	auto[0]	90328	1			T25	59		T1	396		T13	46
bins_for_gpio_bits[31]	auto[1]	auto[1]	2788169	1			T25	1438		T26	49		T1	14971