Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4210806 |
1 |
|
|
T25 |
1118 |
|
T26 |
159 |
|
T1 |
15328 |
| auto[1] |
2019195 |
1 |
|
|
T25 |
954 |
|
T1 |
11432 |
|
T11 |
170 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970860 |
1 |
|
|
T25 |
2041 |
|
T26 |
159 |
|
T1 |
24873 |
| auto[1] |
259141 |
1 |
|
|
T25 |
31 |
|
T1 |
1887 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4214865 |
1 |
|
|
T25 |
1063 |
|
T26 |
159 |
|
T1 |
14331 |
| auto[1] |
2015136 |
1 |
|
|
T25 |
1009 |
|
T1 |
12429 |
|
T11 |
180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
882096 |
1 |
|
|
T25 |
451 |
|
T1 |
5769 |
|
T11 |
84 |
| auto[1] |
auto[0] |
auto[1] |
130711 |
1 |
|
|
T25 |
19 |
|
T1 |
1057 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
873899 |
1 |
|
|
T25 |
527 |
|
T1 |
4773 |
|
T11 |
86 |
| auto[1] |
auto[1] |
auto[1] |
128430 |
1 |
|
|
T25 |
12 |
|
T1 |
830 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215431 |
1 |
|
|
T25 |
919 |
|
T26 |
159 |
|
T1 |
14315 |
| auto[1] |
2014570 |
1 |
|
|
T25 |
1153 |
|
T1 |
12445 |
|
T11 |
174 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5973379 |
1 |
|
|
T25 |
2043 |
|
T26 |
159 |
|
T1 |
25085 |
| auto[1] |
256622 |
1 |
|
|
T25 |
29 |
|
T1 |
1675 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4226510 |
1 |
|
|
T25 |
1074 |
|
T26 |
159 |
|
T1 |
15583 |
| auto[1] |
2003491 |
1 |
|
|
T25 |
998 |
|
T1 |
11177 |
|
T11 |
175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
878090 |
1 |
|
|
T25 |
341 |
|
T1 |
4725 |
|
T11 |
77 |
| auto[1] |
auto[0] |
auto[1] |
128873 |
1 |
|
|
T25 |
7 |
|
T1 |
816 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
868779 |
1 |
|
|
T25 |
628 |
|
T1 |
4777 |
|
T11 |
88 |
| auto[1] |
auto[1] |
auto[1] |
127749 |
1 |
|
|
T25 |
22 |
|
T1 |
859 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213490 |
1 |
|
|
T25 |
1047 |
|
T26 |
159 |
|
T1 |
14562 |
| auto[1] |
2016511 |
1 |
|
|
T25 |
1025 |
|
T1 |
12198 |
|
T11 |
175 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971647 |
1 |
|
|
T25 |
2037 |
|
T26 |
159 |
|
T1 |
24742 |
| auto[1] |
258354 |
1 |
|
|
T25 |
35 |
|
T1 |
2018 |
|
T11 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4216922 |
1 |
|
|
T25 |
1096 |
|
T26 |
159 |
|
T1 |
13853 |
| auto[1] |
2013079 |
1 |
|
|
T25 |
976 |
|
T1 |
12907 |
|
T11 |
108 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
880240 |
1 |
|
|
T25 |
461 |
|
T1 |
5202 |
|
T11 |
43 |
| auto[1] |
auto[0] |
auto[1] |
130385 |
1 |
|
|
T25 |
16 |
|
T1 |
967 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
874485 |
1 |
|
|
T25 |
480 |
|
T1 |
5687 |
|
T11 |
54 |
| auto[1] |
auto[1] |
auto[1] |
127969 |
1 |
|
|
T25 |
19 |
|
T1 |
1051 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4216301 |
1 |
|
|
T25 |
944 |
|
T26 |
159 |
|
T1 |
15496 |
| auto[1] |
2013700 |
1 |
|
|
T25 |
1128 |
|
T1 |
11264 |
|
T11 |
187 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5969637 |
1 |
|
|
T25 |
2037 |
|
T26 |
159 |
|
T1 |
24857 |
| auto[1] |
260364 |
1 |
|
|
T25 |
35 |
|
T1 |
1903 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4206076 |
1 |
|
|
T25 |
1068 |
|
T26 |
159 |
|
T1 |
14690 |
| auto[1] |
2023925 |
1 |
|
|
T25 |
1004 |
|
T1 |
12070 |
|
T11 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
880348 |
1 |
|
|
T25 |
444 |
|
T1 |
5453 |
|
T11 |
68 |
| auto[1] |
auto[0] |
auto[1] |
129602 |
1 |
|
|
T25 |
15 |
|
T1 |
1008 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
883213 |
1 |
|
|
T25 |
525 |
|
T1 |
4714 |
|
T11 |
102 |
| auto[1] |
auto[1] |
auto[1] |
130762 |
1 |
|
|
T25 |
20 |
|
T1 |
895 |
|
T11 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4217596 |
1 |
|
|
T25 |
1013 |
|
T26 |
159 |
|
T1 |
15243 |
| auto[1] |
2012405 |
1 |
|
|
T25 |
1059 |
|
T1 |
11517 |
|
T11 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971457 |
1 |
|
|
T25 |
2036 |
|
T26 |
159 |
|
T1 |
24818 |
| auto[1] |
258544 |
1 |
|
|
T25 |
36 |
|
T1 |
1942 |
|
T11 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4211977 |
1 |
|
|
T25 |
1051 |
|
T26 |
159 |
|
T1 |
14371 |
| auto[1] |
2018024 |
1 |
|
|
T25 |
1021 |
|
T1 |
12389 |
|
T11 |
185 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
879638 |
1 |
|
|
T25 |
489 |
|
T1 |
5335 |
|
T11 |
93 |
| auto[1] |
auto[0] |
auto[1] |
129502 |
1 |
|
|
T25 |
17 |
|
T1 |
1021 |
|
T11 |
10 |
| auto[1] |
auto[1] |
auto[0] |
879842 |
1 |
|
|
T25 |
496 |
|
T1 |
5112 |
|
T11 |
78 |
| auto[1] |
auto[1] |
auto[1] |
129042 |
1 |
|
|
T25 |
19 |
|
T1 |
921 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213598 |
1 |
|
|
T25 |
1148 |
|
T26 |
159 |
|
T1 |
15775 |
| auto[1] |
2016403 |
1 |
|
|
T25 |
924 |
|
T1 |
10985 |
|
T11 |
177 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5973324 |
1 |
|
|
T25 |
2038 |
|
T26 |
159 |
|
T1 |
24976 |
| auto[1] |
256677 |
1 |
|
|
T25 |
34 |
|
T1 |
1784 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4223850 |
1 |
|
|
T25 |
959 |
|
T26 |
159 |
|
T1 |
14810 |
| auto[1] |
2006151 |
1 |
|
|
T25 |
1113 |
|
T1 |
11950 |
|
T11 |
195 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
875765 |
1 |
|
|
T25 |
622 |
|
T1 |
5260 |
|
T11 |
85 |
| auto[1] |
auto[0] |
auto[1] |
129276 |
1 |
|
|
T25 |
23 |
|
T1 |
954 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
873709 |
1 |
|
|
T25 |
457 |
|
T1 |
4906 |
|
T11 |
100 |
| auto[1] |
auto[1] |
auto[1] |
127401 |
1 |
|
|
T25 |
11 |
|
T1 |
830 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4202522 |
1 |
|
|
T25 |
1118 |
|
T26 |
159 |
|
T1 |
16085 |
| auto[1] |
2027479 |
1 |
|
|
T25 |
954 |
|
T1 |
10675 |
|
T11 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970095 |
1 |
|
|
T25 |
2028 |
|
T26 |
159 |
|
T1 |
24854 |
| auto[1] |
259906 |
1 |
|
|
T25 |
44 |
|
T1 |
1906 |
|
T11 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4199847 |
1 |
|
|
T25 |
1040 |
|
T26 |
159 |
|
T1 |
14260 |
| auto[1] |
2030154 |
1 |
|
|
T25 |
1032 |
|
T1 |
12500 |
|
T11 |
99 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
885457 |
1 |
|
|
T25 |
492 |
|
T1 |
6090 |
|
T11 |
48 |
| auto[1] |
auto[0] |
auto[1] |
130071 |
1 |
|
|
T25 |
29 |
|
T1 |
1102 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
884791 |
1 |
|
|
T25 |
496 |
|
T1 |
4504 |
|
T11 |
46 |
| auto[1] |
auto[1] |
auto[1] |
129835 |
1 |
|
|
T25 |
15 |
|
T1 |
804 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4216381 |
1 |
|
|
T25 |
960 |
|
T26 |
159 |
|
T1 |
16019 |
| auto[1] |
2013620 |
1 |
|
|
T25 |
1112 |
|
T1 |
10741 |
|
T11 |
134 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5969674 |
1 |
|
|
T25 |
2030 |
|
T26 |
159 |
|
T1 |
24934 |
| auto[1] |
260327 |
1 |
|
|
T25 |
42 |
|
T1 |
1826 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4207456 |
1 |
|
|
T25 |
967 |
|
T26 |
159 |
|
T1 |
14929 |
| auto[1] |
2022545 |
1 |
|
|
T25 |
1105 |
|
T1 |
11831 |
|
T11 |
160 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
888904 |
1 |
|
|
T25 |
478 |
|
T1 |
5680 |
|
T11 |
90 |
| auto[1] |
auto[0] |
auto[1] |
131277 |
1 |
|
|
T25 |
15 |
|
T1 |
1025 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
873314 |
1 |
|
|
T25 |
585 |
|
T1 |
4325 |
|
T11 |
60 |
| auto[1] |
auto[1] |
auto[1] |
129050 |
1 |
|
|
T25 |
27 |
|
T1 |
801 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4225173 |
1 |
|
|
T25 |
938 |
|
T26 |
159 |
|
T1 |
15453 |
| auto[1] |
2004828 |
1 |
|
|
T25 |
1134 |
|
T1 |
11307 |
|
T11 |
142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971298 |
1 |
|
|
T25 |
2030 |
|
T26 |
159 |
|
T1 |
24931 |
| auto[1] |
258703 |
1 |
|
|
T25 |
42 |
|
T1 |
1829 |
|
T11 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215713 |
1 |
|
|
T25 |
1069 |
|
T26 |
159 |
|
T1 |
14511 |
| auto[1] |
2014288 |
1 |
|
|
T25 |
1003 |
|
T1 |
12249 |
|
T11 |
114 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
890880 |
1 |
|
|
T25 |
474 |
|
T1 |
5286 |
|
T11 |
44 |
| auto[1] |
auto[0] |
auto[1] |
131856 |
1 |
|
|
T25 |
21 |
|
T1 |
935 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[0] |
864705 |
1 |
|
|
T25 |
487 |
|
T1 |
5134 |
|
T11 |
63 |
| auto[1] |
auto[1] |
auto[1] |
126847 |
1 |
|
|
T25 |
21 |
|
T1 |
894 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4210772 |
1 |
|
|
T25 |
1032 |
|
T26 |
159 |
|
T1 |
14922 |
| auto[1] |
2019229 |
1 |
|
|
T25 |
1040 |
|
T1 |
11838 |
|
T11 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5973900 |
1 |
|
|
T25 |
2043 |
|
T26 |
159 |
|
T1 |
24939 |
| auto[1] |
256101 |
1 |
|
|
T25 |
29 |
|
T1 |
1821 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4230833 |
1 |
|
|
T25 |
1229 |
|
T26 |
159 |
|
T1 |
14772 |
| auto[1] |
1999168 |
1 |
|
|
T25 |
843 |
|
T1 |
11988 |
|
T11 |
163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
873022 |
1 |
|
|
T25 |
397 |
|
T1 |
5466 |
|
T11 |
67 |
| auto[1] |
auto[0] |
auto[1] |
128194 |
1 |
|
|
T25 |
14 |
|
T1 |
932 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[0] |
870045 |
1 |
|
|
T25 |
417 |
|
T1 |
4701 |
|
T11 |
86 |
| auto[1] |
auto[1] |
auto[1] |
127907 |
1 |
|
|
T25 |
15 |
|
T1 |
889 |
|
T11 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4224021 |
1 |
|
|
T25 |
967 |
|
T26 |
159 |
|
T1 |
15602 |
| auto[1] |
2005980 |
1 |
|
|
T25 |
1105 |
|
T1 |
11158 |
|
T11 |
203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970873 |
1 |
|
|
T25 |
2046 |
|
T26 |
159 |
|
T1 |
24868 |
| auto[1] |
259128 |
1 |
|
|
T25 |
26 |
|
T1 |
1892 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4212820 |
1 |
|
|
T25 |
1009 |
|
T26 |
159 |
|
T1 |
14574 |
| auto[1] |
2017181 |
1 |
|
|
T25 |
1063 |
|
T1 |
12186 |
|
T11 |
161 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
888439 |
1 |
|
|
T25 |
400 |
|
T1 |
5184 |
|
T11 |
53 |
| auto[1] |
auto[0] |
auto[1] |
130865 |
1 |
|
|
T25 |
3 |
|
T1 |
915 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
869614 |
1 |
|
|
T25 |
637 |
|
T1 |
5110 |
|
T11 |
95 |
| auto[1] |
auto[1] |
auto[1] |
128263 |
1 |
|
|
T25 |
23 |
|
T1 |
977 |
|
T11 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4200456 |
1 |
|
|
T25 |
1130 |
|
T26 |
159 |
|
T1 |
14458 |
| auto[1] |
2029545 |
1 |
|
|
T25 |
942 |
|
T1 |
12302 |
|
T11 |
143 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971715 |
1 |
|
|
T25 |
2043 |
|
T26 |
159 |
|
T1 |
24954 |
| auto[1] |
258286 |
1 |
|
|
T25 |
29 |
|
T1 |
1806 |
|
T11 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4214801 |
1 |
|
|
T25 |
1215 |
|
T26 |
159 |
|
T1 |
15178 |
| auto[1] |
2015200 |
1 |
|
|
T25 |
857 |
|
T1 |
11582 |
|
T11 |
92 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
874969 |
1 |
|
|
T25 |
416 |
|
T1 |
5043 |
|
T11 |
51 |
| auto[1] |
auto[0] |
auto[1] |
128529 |
1 |
|
|
T25 |
21 |
|
T1 |
909 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
881945 |
1 |
|
|
T25 |
412 |
|
T1 |
4733 |
|
T11 |
34 |
| auto[1] |
auto[1] |
auto[1] |
129757 |
1 |
|
|
T25 |
8 |
|
T1 |
897 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4209592 |
1 |
|
|
T25 |
923 |
|
T26 |
159 |
|
T1 |
15848 |
| auto[1] |
2020409 |
1 |
|
|
T25 |
1149 |
|
T1 |
10912 |
|
T11 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5972963 |
1 |
|
|
T25 |
2031 |
|
T26 |
159 |
|
T1 |
24940 |
| auto[1] |
257038 |
1 |
|
|
T25 |
41 |
|
T1 |
1820 |
|
T11 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4220068 |
1 |
|
|
T25 |
969 |
|
T26 |
159 |
|
T1 |
14578 |
| auto[1] |
2009933 |
1 |
|
|
T25 |
1103 |
|
T1 |
12182 |
|
T11 |
171 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
877362 |
1 |
|
|
T25 |
438 |
|
T1 |
5980 |
|
T11 |
56 |
| auto[1] |
auto[0] |
auto[1] |
128744 |
1 |
|
|
T25 |
20 |
|
T1 |
1075 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
875533 |
1 |
|
|
T25 |
624 |
|
T1 |
4382 |
|
T11 |
103 |
| auto[1] |
auto[1] |
auto[1] |
128294 |
1 |
|
|
T25 |
21 |
|
T1 |
745 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4208430 |
1 |
|
|
T25 |
1019 |
|
T26 |
159 |
|
T1 |
14201 |
| auto[1] |
2021571 |
1 |
|
|
T25 |
1053 |
|
T1 |
12559 |
|
T11 |
116 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5972558 |
1 |
|
|
T25 |
2026 |
|
T26 |
159 |
|
T1 |
24934 |
| auto[1] |
257443 |
1 |
|
|
T25 |
46 |
|
T1 |
1826 |
|
T11 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4221287 |
1 |
|
|
T25 |
1006 |
|
T26 |
159 |
|
T1 |
14496 |
| auto[1] |
2008714 |
1 |
|
|
T25 |
1066 |
|
T1 |
12264 |
|
T11 |
224 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
875022 |
1 |
|
|
T25 |
534 |
|
T1 |
4508 |
|
T11 |
137 |
| auto[1] |
auto[0] |
auto[1] |
128837 |
1 |
|
|
T25 |
25 |
|
T1 |
766 |
|
T11 |
7 |
| auto[1] |
auto[1] |
auto[0] |
876249 |
1 |
|
|
T25 |
486 |
|
T1 |
5930 |
|
T11 |
73 |
| auto[1] |
auto[1] |
auto[1] |
128606 |
1 |
|
|
T25 |
21 |
|
T1 |
1060 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4222238 |
1 |
|
|
T25 |
864 |
|
T26 |
159 |
|
T1 |
14826 |
| auto[1] |
2007763 |
1 |
|
|
T25 |
1208 |
|
T1 |
11934 |
|
T11 |
172 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5974539 |
1 |
|
|
T25 |
2022 |
|
T26 |
159 |
|
T1 |
24830 |
| auto[1] |
255462 |
1 |
|
|
T25 |
50 |
|
T1 |
1930 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4230473 |
1 |
|
|
T25 |
937 |
|
T26 |
159 |
|
T1 |
14393 |
| auto[1] |
1999528 |
1 |
|
|
T25 |
1135 |
|
T1 |
12367 |
|
T11 |
160 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
880857 |
1 |
|
|
T25 |
407 |
|
T1 |
5331 |
|
T11 |
73 |
| auto[1] |
auto[0] |
auto[1] |
129582 |
1 |
|
|
T25 |
18 |
|
T1 |
957 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
863209 |
1 |
|
|
T25 |
678 |
|
T1 |
5106 |
|
T11 |
78 |
| auto[1] |
auto[1] |
auto[1] |
125880 |
1 |
|
|
T25 |
32 |
|
T1 |
973 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4203544 |
1 |
|
|
T25 |
1048 |
|
T26 |
159 |
|
T1 |
14009 |
| auto[1] |
2026457 |
1 |
|
|
T25 |
1024 |
|
T1 |
12751 |
|
T11 |
119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5973406 |
1 |
|
|
T25 |
2022 |
|
T26 |
159 |
|
T1 |
25015 |
| auto[1] |
256595 |
1 |
|
|
T25 |
50 |
|
T1 |
1745 |
|
T11 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4221426 |
1 |
|
|
T25 |
832 |
|
T26 |
159 |
|
T1 |
15455 |
| auto[1] |
2008575 |
1 |
|
|
T25 |
1240 |
|
T1 |
11305 |
|
T11 |
87 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
875050 |
1 |
|
|
T25 |
636 |
|
T1 |
4664 |
|
T11 |
54 |
| auto[1] |
auto[0] |
auto[1] |
128210 |
1 |
|
|
T25 |
24 |
|
T1 |
848 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[0] |
876930 |
1 |
|
|
T25 |
554 |
|
T1 |
4896 |
|
T11 |
30 |
| auto[1] |
auto[1] |
auto[1] |
128385 |
1 |
|
|
T25 |
26 |
|
T1 |
897 |
|
T11 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215033 |
1 |
|
|
T25 |
970 |
|
T26 |
159 |
|
T1 |
15432 |
| auto[1] |
2014968 |
1 |
|
|
T25 |
1102 |
|
T1 |
11328 |
|
T11 |
152 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970831 |
1 |
|
|
T25 |
2037 |
|
T26 |
159 |
|
T1 |
24882 |
| auto[1] |
259170 |
1 |
|
|
T25 |
35 |
|
T1 |
1878 |
|
T11 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4210558 |
1 |
|
|
T25 |
1212 |
|
T26 |
159 |
|
T1 |
14896 |
| auto[1] |
2019443 |
1 |
|
|
T25 |
860 |
|
T1 |
11864 |
|
T11 |
184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
887016 |
1 |
|
|
T25 |
375 |
|
T1 |
5357 |
|
T11 |
101 |
| auto[1] |
auto[0] |
auto[1] |
130992 |
1 |
|
|
T25 |
20 |
|
T1 |
1014 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
873257 |
1 |
|
|
T25 |
450 |
|
T1 |
4629 |
|
T11 |
72 |
| auto[1] |
auto[1] |
auto[1] |
128178 |
1 |
|
|
T25 |
15 |
|
T1 |
864 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4195997 |
1 |
|
|
T25 |
1048 |
|
T26 |
159 |
|
T1 |
15071 |
| auto[1] |
2034004 |
1 |
|
|
T25 |
1024 |
|
T1 |
11689 |
|
T11 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5972490 |
1 |
|
|
T25 |
2043 |
|
T26 |
159 |
|
T1 |
25096 |
| auto[1] |
257511 |
1 |
|
|
T25 |
29 |
|
T1 |
1664 |
|
T11 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4216067 |
1 |
|
|
T25 |
1170 |
|
T26 |
159 |
|
T1 |
15674 |
| auto[1] |
2013934 |
1 |
|
|
T25 |
902 |
|
T1 |
11086 |
|
T11 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
874629 |
1 |
|
|
T25 |
444 |
|
T1 |
4711 |
|
T11 |
47 |
| auto[1] |
auto[0] |
auto[1] |
128307 |
1 |
|
|
T25 |
18 |
|
T1 |
843 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
881794 |
1 |
|
|
T25 |
429 |
|
T1 |
4711 |
|
T11 |
50 |
| auto[1] |
auto[1] |
auto[1] |
129204 |
1 |
|
|
T25 |
11 |
|
T1 |
821 |
|
T11 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4216785 |
1 |
|
|
T25 |
1187 |
|
T26 |
159 |
|
T1 |
14525 |
| auto[1] |
2013216 |
1 |
|
|
T25 |
885 |
|
T1 |
12235 |
|
T11 |
125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5973170 |
1 |
|
|
T25 |
2033 |
|
T26 |
159 |
|
T1 |
24944 |
| auto[1] |
256831 |
1 |
|
|
T25 |
39 |
|
T1 |
1816 |
|
T11 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4226360 |
1 |
|
|
T25 |
1227 |
|
T26 |
159 |
|
T1 |
14757 |
| auto[1] |
2003641 |
1 |
|
|
T25 |
845 |
|
T1 |
12003 |
|
T11 |
151 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
885223 |
1 |
|
|
T25 |
470 |
|
T1 |
5045 |
|
T11 |
78 |
| auto[1] |
auto[0] |
auto[1] |
130787 |
1 |
|
|
T25 |
23 |
|
T1 |
845 |
|
T11 |
8 |
| auto[1] |
auto[1] |
auto[0] |
861587 |
1 |
|
|
T25 |
336 |
|
T1 |
5142 |
|
T11 |
61 |
| auto[1] |
auto[1] |
auto[1] |
126044 |
1 |
|
|
T25 |
16 |
|
T1 |
971 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4218079 |
1 |
|
|
T25 |
1030 |
|
T26 |
159 |
|
T1 |
15477 |
| auto[1] |
2011922 |
1 |
|
|
T25 |
1042 |
|
T1 |
11283 |
|
T11 |
114 |