Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4194875 |
1 |
|
|
T25 |
982 |
|
T26 |
159 |
|
T1 |
13833 |
| auto[1] |
2035126 |
1 |
|
|
T25 |
1090 |
|
T1 |
12927 |
|
T11 |
143 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5975456 |
1 |
|
|
T25 |
2031 |
|
T26 |
159 |
|
T1 |
25186 |
| auto[1] |
254545 |
1 |
|
|
T25 |
41 |
|
T1 |
1574 |
|
T11 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4236197 |
1 |
|
|
T25 |
1075 |
|
T26 |
159 |
|
T1 |
16132 |
| auto[1] |
1993804 |
1 |
|
|
T25 |
997 |
|
T1 |
10628 |
|
T11 |
183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
864446 |
1 |
|
|
T25 |
469 |
|
T1 |
4552 |
|
T11 |
107 |
| auto[1] |
auto[0] |
auto[1] |
126839 |
1 |
|
|
T25 |
17 |
|
T1 |
833 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
874813 |
1 |
|
|
T25 |
487 |
|
T1 |
4502 |
|
T11 |
68 |
| auto[1] |
auto[1] |
auto[1] |
127706 |
1 |
|
|
T25 |
24 |
|
T1 |
741 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |