Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4194170 |
1 |
|
|
T25 |
983 |
|
T26 |
159 |
|
T1 |
15132 |
| auto[1] |
2035831 |
1 |
|
|
T25 |
1089 |
|
T1 |
11628 |
|
T11 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970671 |
1 |
|
|
T25 |
2032 |
|
T26 |
159 |
|
T1 |
25138 |
| auto[1] |
259330 |
1 |
|
|
T25 |
40 |
|
T1 |
1622 |
|
T11 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213301 |
1 |
|
|
T25 |
942 |
|
T26 |
159 |
|
T1 |
15910 |
| auto[1] |
2016700 |
1 |
|
|
T25 |
1130 |
|
T1 |
10850 |
|
T11 |
115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
865629 |
1 |
|
|
T25 |
577 |
|
T1 |
4566 |
|
T11 |
70 |
| auto[1] |
auto[0] |
auto[1] |
127289 |
1 |
|
|
T25 |
24 |
|
T1 |
803 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
891741 |
1 |
|
|
T25 |
513 |
|
T1 |
4662 |
|
T11 |
37 |
| auto[1] |
auto[1] |
auto[1] |
132041 |
1 |
|
|
T25 |
16 |
|
T1 |
819 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |