Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215911 |
1 |
|
|
T25 |
929 |
|
T26 |
159 |
|
T1 |
14670 |
| auto[1] |
2014090 |
1 |
|
|
T25 |
1143 |
|
T1 |
12090 |
|
T11 |
168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5972085 |
1 |
|
|
T25 |
2039 |
|
T26 |
159 |
|
T1 |
24833 |
| auto[1] |
257916 |
1 |
|
|
T25 |
33 |
|
T1 |
1927 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4210040 |
1 |
|
|
T25 |
1080 |
|
T26 |
159 |
|
T1 |
13929 |
| auto[1] |
2019961 |
1 |
|
|
T25 |
992 |
|
T1 |
12831 |
|
T11 |
149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
885731 |
1 |
|
|
T25 |
422 |
|
T1 |
5354 |
|
T11 |
69 |
| auto[1] |
auto[0] |
auto[1] |
129811 |
1 |
|
|
T25 |
22 |
|
T1 |
931 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[0] |
876314 |
1 |
|
|
T25 |
537 |
|
T1 |
5550 |
|
T11 |
70 |
| auto[1] |
auto[1] |
auto[1] |
128105 |
1 |
|
|
T25 |
11 |
|
T1 |
996 |
|
T11 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |