Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213629 |
1 |
|
|
T25 |
933 |
|
T26 |
159 |
|
T1 |
14651 |
| auto[1] |
2016372 |
1 |
|
|
T25 |
1139 |
|
T1 |
12109 |
|
T11 |
146 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971686 |
1 |
|
|
T25 |
2031 |
|
T26 |
159 |
|
T1 |
24854 |
| auto[1] |
258315 |
1 |
|
|
T25 |
41 |
|
T1 |
1906 |
|
T11 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213943 |
1 |
|
|
T25 |
966 |
|
T26 |
159 |
|
T1 |
14369 |
| auto[1] |
2016058 |
1 |
|
|
T25 |
1106 |
|
T1 |
12391 |
|
T11 |
139 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
878183 |
1 |
|
|
T25 |
518 |
|
T1 |
4939 |
|
T11 |
81 |
| auto[1] |
auto[0] |
auto[1] |
129387 |
1 |
|
|
T25 |
19 |
|
T1 |
921 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
879560 |
1 |
|
|
T25 |
547 |
|
T1 |
5546 |
|
T11 |
48 |
| auto[1] |
auto[1] |
auto[1] |
128928 |
1 |
|
|
T25 |
22 |
|
T1 |
985 |
|
T11 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |