Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215431 |
1 |
|
|
T25 |
919 |
|
T26 |
159 |
|
T1 |
14315 |
| auto[1] |
2014570 |
1 |
|
|
T25 |
1153 |
|
T1 |
12445 |
|
T11 |
174 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5284428 |
1 |
|
|
T25 |
1276 |
|
T26 |
159 |
|
T1 |
20178 |
| auto[1] |
945573 |
1 |
|
|
T25 |
796 |
|
T1 |
6582 |
|
T11 |
69 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4212878 |
1 |
|
|
T25 |
1029 |
|
T26 |
159 |
|
T1 |
14808 |
| auto[1] |
2017123 |
1 |
|
|
T25 |
1043 |
|
T1 |
11952 |
|
T11 |
166 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
533457 |
1 |
|
|
T25 |
111 |
|
T1 |
2864 |
|
T11 |
44 |
| auto[1] |
auto[0] |
auto[1] |
474933 |
1 |
|
|
T25 |
403 |
|
T1 |
3381 |
|
T11 |
15 |
| auto[1] |
auto[1] |
auto[0] |
538093 |
1 |
|
|
T25 |
136 |
|
T1 |
2506 |
|
T11 |
53 |
| auto[1] |
auto[1] |
auto[1] |
470640 |
1 |
|
|
T25 |
393 |
|
T1 |
3201 |
|
T11 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |