Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213490 |
1 |
|
|
T25 |
1047 |
|
T26 |
159 |
|
T1 |
14562 |
| auto[1] |
2016511 |
1 |
|
|
T25 |
1025 |
|
T1 |
12198 |
|
T11 |
175 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5293233 |
1 |
|
|
T25 |
1252 |
|
T26 |
159 |
|
T1 |
19599 |
| auto[1] |
936768 |
1 |
|
|
T25 |
820 |
|
T1 |
7161 |
|
T11 |
77 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4223382 |
1 |
|
|
T25 |
1001 |
|
T26 |
159 |
|
T1 |
14401 |
| auto[1] |
2006619 |
1 |
|
|
T25 |
1071 |
|
T1 |
12359 |
|
T11 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
538876 |
1 |
|
|
T25 |
112 |
|
T1 |
2680 |
|
T11 |
25 |
| auto[1] |
auto[0] |
auto[1] |
469934 |
1 |
|
|
T25 |
380 |
|
T1 |
3709 |
|
T11 |
24 |
| auto[1] |
auto[1] |
auto[0] |
530975 |
1 |
|
|
T25 |
139 |
|
T1 |
2518 |
|
T11 |
29 |
| auto[1] |
auto[1] |
auto[1] |
466834 |
1 |
|
|
T25 |
440 |
|
T1 |
3452 |
|
T11 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |