Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4216301 |
1 |
|
|
T25 |
944 |
|
T26 |
159 |
|
T1 |
15496 |
| auto[1] |
2013700 |
1 |
|
|
T25 |
1128 |
|
T1 |
11264 |
|
T11 |
187 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5295664 |
1 |
|
|
T25 |
1282 |
|
T26 |
159 |
|
T1 |
20098 |
| auto[1] |
934337 |
1 |
|
|
T25 |
790 |
|
T1 |
6662 |
|
T11 |
77 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4228076 |
1 |
|
|
T25 |
1105 |
|
T26 |
159 |
|
T1 |
14701 |
| auto[1] |
2001925 |
1 |
|
|
T25 |
967 |
|
T1 |
12059 |
|
T11 |
130 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
536336 |
1 |
|
|
T25 |
76 |
|
T1 |
2711 |
|
T11 |
16 |
| auto[1] |
auto[0] |
auto[1] |
469179 |
1 |
|
|
T25 |
384 |
|
T1 |
3482 |
|
T11 |
31 |
| auto[1] |
auto[1] |
auto[0] |
531252 |
1 |
|
|
T25 |
101 |
|
T1 |
2686 |
|
T11 |
37 |
| auto[1] |
auto[1] |
auto[1] |
465158 |
1 |
|
|
T25 |
406 |
|
T1 |
3180 |
|
T11 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |