Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4217596 |
1 |
|
|
T25 |
1013 |
|
T26 |
159 |
|
T1 |
15243 |
| auto[1] |
2012405 |
1 |
|
|
T25 |
1059 |
|
T1 |
11517 |
|
T11 |
169 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5284508 |
1 |
|
|
T25 |
1305 |
|
T26 |
159 |
|
T1 |
20080 |
| auto[1] |
945493 |
1 |
|
|
T25 |
767 |
|
T1 |
6680 |
|
T11 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4209959 |
1 |
|
|
T25 |
1122 |
|
T26 |
159 |
|
T1 |
14753 |
| auto[1] |
2020042 |
1 |
|
|
T25 |
950 |
|
T1 |
12007 |
|
T11 |
169 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
541402 |
1 |
|
|
T25 |
91 |
|
T1 |
2956 |
|
T11 |
39 |
| auto[1] |
auto[0] |
auto[1] |
472294 |
1 |
|
|
T25 |
340 |
|
T1 |
3674 |
|
T11 |
47 |
| auto[1] |
auto[1] |
auto[0] |
533147 |
1 |
|
|
T25 |
92 |
|
T1 |
2371 |
|
T11 |
55 |
| auto[1] |
auto[1] |
auto[1] |
473199 |
1 |
|
|
T25 |
427 |
|
T1 |
3006 |
|
T11 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |