Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971671 |
1 |
|
|
T25 |
2027 |
|
T26 |
159 |
|
T1 |
24847 |
| auto[1] |
258330 |
1 |
|
|
T25 |
45 |
|
T1 |
1913 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215380 |
1 |
|
|
T25 |
1121 |
|
T26 |
159 |
|
T1 |
14324 |
| auto[1] |
2014621 |
1 |
|
|
T25 |
951 |
|
T1 |
12436 |
|
T11 |
157 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
883572 |
1 |
|
|
T25 |
464 |
|
T1 |
5947 |
|
T11 |
85 |
| auto[1] |
auto[0] |
auto[1] |
129832 |
1 |
|
|
T25 |
23 |
|
T1 |
1077 |
|
T11 |
9 |
| auto[1] |
auto[1] |
auto[0] |
872719 |
1 |
|
|
T25 |
442 |
|
T1 |
4576 |
|
T11 |
59 |
| auto[1] |
auto[1] |
auto[1] |
128498 |
1 |
|
|
T25 |
22 |
|
T1 |
836 |
|
T11 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |