Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4213598 |
1 |
|
|
T25 |
1148 |
|
T26 |
159 |
|
T1 |
15775 |
| auto[1] |
2016403 |
1 |
|
|
T25 |
924 |
|
T1 |
10985 |
|
T11 |
177 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5289569 |
1 |
|
|
T25 |
1112 |
|
T26 |
159 |
|
T1 |
19888 |
| auto[1] |
940432 |
1 |
|
|
T25 |
960 |
|
T1 |
6872 |
|
T11 |
98 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4217950 |
1 |
|
|
T25 |
904 |
|
T26 |
159 |
|
T1 |
14857 |
| auto[1] |
2012051 |
1 |
|
|
T25 |
1168 |
|
T1 |
11903 |
|
T11 |
175 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
540603 |
1 |
|
|
T25 |
128 |
|
T1 |
2693 |
|
T11 |
47 |
| auto[1] |
auto[0] |
auto[1] |
471963 |
1 |
|
|
T25 |
587 |
|
T1 |
3846 |
|
T11 |
52 |
| auto[1] |
auto[1] |
auto[0] |
531016 |
1 |
|
|
T25 |
80 |
|
T1 |
2338 |
|
T11 |
30 |
| auto[1] |
auto[1] |
auto[1] |
468469 |
1 |
|
|
T25 |
373 |
|
T1 |
3026 |
|
T11 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |