Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4202522 |
1 |
|
|
T25 |
1118 |
|
T26 |
159 |
|
T1 |
16085 |
| auto[1] |
2027479 |
1 |
|
|
T25 |
954 |
|
T1 |
10675 |
|
T11 |
193 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5286649 |
1 |
|
|
T25 |
1305 |
|
T26 |
159 |
|
T1 |
20087 |
| auto[1] |
943352 |
1 |
|
|
T25 |
767 |
|
T1 |
6673 |
|
T11 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4210944 |
1 |
|
|
T25 |
999 |
|
T26 |
159 |
|
T1 |
14780 |
| auto[1] |
2019057 |
1 |
|
|
T25 |
1073 |
|
T1 |
11980 |
|
T11 |
139 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
536162 |
1 |
|
|
T25 |
171 |
|
T1 |
2788 |
|
T11 |
21 |
| auto[1] |
auto[0] |
auto[1] |
472423 |
1 |
|
|
T25 |
393 |
|
T1 |
3593 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[0] |
539543 |
1 |
|
|
T25 |
135 |
|
T1 |
2519 |
|
T11 |
58 |
| auto[1] |
auto[1] |
auto[1] |
470929 |
1 |
|
|
T25 |
374 |
|
T1 |
3080 |
|
T11 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |