Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4225173 |
1 |
|
|
T25 |
938 |
|
T26 |
159 |
|
T1 |
15453 |
| auto[1] |
2004828 |
1 |
|
|
T25 |
1134 |
|
T1 |
11307 |
|
T11 |
142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5284849 |
1 |
|
|
T25 |
1289 |
|
T26 |
159 |
|
T1 |
20237 |
| auto[1] |
945152 |
1 |
|
|
T25 |
783 |
|
T1 |
6523 |
|
T11 |
79 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4211611 |
1 |
|
|
T25 |
1021 |
|
T26 |
159 |
|
T1 |
15371 |
| auto[1] |
2018390 |
1 |
|
|
T25 |
1051 |
|
T1 |
11389 |
|
T11 |
138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
540059 |
1 |
|
|
T25 |
99 |
|
T1 |
2605 |
|
T11 |
31 |
| auto[1] |
auto[0] |
auto[1] |
476306 |
1 |
|
|
T25 |
378 |
|
T1 |
3505 |
|
T11 |
50 |
| auto[1] |
auto[1] |
auto[0] |
533179 |
1 |
|
|
T25 |
169 |
|
T1 |
2261 |
|
T11 |
28 |
| auto[1] |
auto[1] |
auto[1] |
468846 |
1 |
|
|
T25 |
405 |
|
T1 |
3018 |
|
T11 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |