Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4208430 |
1 |
|
|
T25 |
1019 |
|
T26 |
159 |
|
T1 |
14201 |
| auto[1] |
2021571 |
1 |
|
|
T25 |
1053 |
|
T1 |
12559 |
|
T11 |
116 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5297121 |
1 |
|
|
T25 |
1143 |
|
T26 |
159 |
|
T1 |
19526 |
| auto[1] |
932880 |
1 |
|
|
T25 |
929 |
|
T1 |
7234 |
|
T11 |
68 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4231316 |
1 |
|
|
T25 |
920 |
|
T26 |
159 |
|
T1 |
14047 |
| auto[1] |
1998685 |
1 |
|
|
T25 |
1152 |
|
T1 |
12713 |
|
T11 |
125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
529819 |
1 |
|
|
T25 |
131 |
|
T1 |
2615 |
|
T11 |
27 |
| auto[1] |
auto[0] |
auto[1] |
466430 |
1 |
|
|
T25 |
415 |
|
T1 |
3429 |
|
T11 |
51 |
| auto[1] |
auto[1] |
auto[0] |
535986 |
1 |
|
|
T25 |
92 |
|
T1 |
2864 |
|
T11 |
30 |
| auto[1] |
auto[1] |
auto[1] |
466450 |
1 |
|
|
T25 |
514 |
|
T1 |
3805 |
|
T11 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |