Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4222238 |
1 |
|
|
T25 |
864 |
|
T26 |
159 |
|
T1 |
14826 |
| auto[1] |
2007763 |
1 |
|
|
T25 |
1208 |
|
T1 |
11934 |
|
T11 |
172 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5293687 |
1 |
|
|
T25 |
1347 |
|
T26 |
159 |
|
T1 |
19980 |
| auto[1] |
936314 |
1 |
|
|
T25 |
725 |
|
T1 |
6780 |
|
T11 |
87 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4228632 |
1 |
|
|
T25 |
1094 |
|
T26 |
159 |
|
T1 |
14900 |
| auto[1] |
2001369 |
1 |
|
|
T25 |
978 |
|
T1 |
11860 |
|
T11 |
162 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
538292 |
1 |
|
|
T25 |
130 |
|
T1 |
2757 |
|
T11 |
31 |
| auto[1] |
auto[0] |
auto[1] |
472930 |
1 |
|
|
T25 |
274 |
|
T1 |
3648 |
|
T11 |
37 |
| auto[1] |
auto[1] |
auto[0] |
526763 |
1 |
|
|
T25 |
123 |
|
T1 |
2323 |
|
T11 |
44 |
| auto[1] |
auto[1] |
auto[1] |
463384 |
1 |
|
|
T25 |
451 |
|
T1 |
3132 |
|
T11 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |