Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4203544 |
1 |
|
|
T25 |
1048 |
|
T26 |
159 |
|
T1 |
14009 |
| auto[1] |
2026457 |
1 |
|
|
T25 |
1024 |
|
T1 |
12751 |
|
T11 |
119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5283393 |
1 |
|
|
T25 |
1346 |
|
T26 |
159 |
|
T1 |
20610 |
| auto[1] |
946608 |
1 |
|
|
T25 |
726 |
|
T1 |
6150 |
|
T11 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4203919 |
1 |
|
|
T25 |
1097 |
|
T26 |
159 |
|
T1 |
15975 |
| auto[1] |
2026082 |
1 |
|
|
T25 |
975 |
|
T1 |
10785 |
|
T11 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
542224 |
1 |
|
|
T25 |
154 |
|
T1 |
2290 |
|
T11 |
20 |
| auto[1] |
auto[0] |
auto[1] |
474455 |
1 |
|
|
T25 |
355 |
|
T1 |
3146 |
|
T11 |
25 |
| auto[1] |
auto[1] |
auto[0] |
537250 |
1 |
|
|
T25 |
95 |
|
T1 |
2345 |
|
T11 |
41 |
| auto[1] |
auto[1] |
auto[1] |
472153 |
1 |
|
|
T25 |
371 |
|
T1 |
3004 |
|
T11 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |