Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215033 |
1 |
|
|
T25 |
970 |
|
T26 |
159 |
|
T1 |
15432 |
| auto[1] |
2014968 |
1 |
|
|
T25 |
1102 |
|
T1 |
11328 |
|
T11 |
152 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5287022 |
1 |
|
|
T25 |
1371 |
|
T26 |
159 |
|
T1 |
19574 |
| auto[1] |
942979 |
1 |
|
|
T25 |
701 |
|
T1 |
7186 |
|
T11 |
47 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4210341 |
1 |
|
|
T25 |
1087 |
|
T26 |
159 |
|
T1 |
14055 |
| auto[1] |
2019660 |
1 |
|
|
T25 |
985 |
|
T1 |
12705 |
|
T11 |
84 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
540189 |
1 |
|
|
T25 |
136 |
|
T1 |
3017 |
|
T11 |
20 |
| auto[1] |
auto[0] |
auto[1] |
471089 |
1 |
|
|
T25 |
325 |
|
T1 |
3961 |
|
T11 |
24 |
| auto[1] |
auto[1] |
auto[0] |
536492 |
1 |
|
|
T25 |
148 |
|
T1 |
2502 |
|
T11 |
17 |
| auto[1] |
auto[1] |
auto[1] |
471890 |
1 |
|
|
T25 |
376 |
|
T1 |
3225 |
|
T11 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |