Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4206109 |
1 |
|
|
T25 |
1086 |
|
T26 |
159 |
|
T1 |
16668 |
| auto[1] |
2023892 |
1 |
|
|
T25 |
986 |
|
T1 |
10092 |
|
T11 |
174 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5971501 |
1 |
|
|
T25 |
2037 |
|
T26 |
159 |
|
T1 |
24849 |
| auto[1] |
258500 |
1 |
|
|
T25 |
35 |
|
T1 |
1911 |
|
T11 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4212958 |
1 |
|
|
T25 |
1086 |
|
T26 |
159 |
|
T1 |
14644 |
| auto[1] |
2017043 |
1 |
|
|
T25 |
986 |
|
T1 |
12116 |
|
T11 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
876036 |
1 |
|
|
T25 |
495 |
|
T1 |
5656 |
|
T11 |
44 |
| auto[1] |
auto[0] |
auto[1] |
129375 |
1 |
|
|
T25 |
22 |
|
T1 |
1084 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[0] |
882507 |
1 |
|
|
T25 |
456 |
|
T1 |
4549 |
|
T11 |
76 |
| auto[1] |
auto[1] |
auto[1] |
129125 |
1 |
|
|
T25 |
13 |
|
T1 |
827 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |