Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4209126 |
1 |
|
|
T25 |
989 |
|
T26 |
159 |
|
T1 |
15601 |
| auto[1] |
2020875 |
1 |
|
|
T25 |
1083 |
|
T1 |
11159 |
|
T11 |
148 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970883 |
1 |
|
|
T25 |
2043 |
|
T26 |
159 |
|
T1 |
24842 |
| auto[1] |
259118 |
1 |
|
|
T25 |
29 |
|
T1 |
1918 |
|
T11 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4214078 |
1 |
|
|
T25 |
1191 |
|
T26 |
159 |
|
T1 |
14056 |
| auto[1] |
2015923 |
1 |
|
|
T25 |
881 |
|
T1 |
12704 |
|
T11 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
876423 |
1 |
|
|
T25 |
418 |
|
T1 |
5713 |
|
T11 |
55 |
| auto[1] |
auto[0] |
auto[1] |
129273 |
1 |
|
|
T25 |
14 |
|
T1 |
1042 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[0] |
880382 |
1 |
|
|
T25 |
434 |
|
T1 |
5073 |
|
T11 |
38 |
| auto[1] |
auto[1] |
auto[1] |
129845 |
1 |
|
|
T25 |
15 |
|
T1 |
876 |
|
T11 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |