Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4197766 |
1 |
|
|
T25 |
920 |
|
T26 |
159 |
|
T1 |
14762 |
| auto[1] |
2032235 |
1 |
|
|
T25 |
1152 |
|
T1 |
11998 |
|
T11 |
175 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970097 |
1 |
|
|
T25 |
2039 |
|
T26 |
159 |
|
T1 |
24760 |
| auto[1] |
259904 |
1 |
|
|
T25 |
33 |
|
T1 |
2000 |
|
T11 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4208484 |
1 |
|
|
T25 |
1121 |
|
T26 |
159 |
|
T1 |
14194 |
| auto[1] |
2021517 |
1 |
|
|
T25 |
951 |
|
T1 |
12566 |
|
T11 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
878469 |
1 |
|
|
T25 |
387 |
|
T1 |
5079 |
|
T11 |
44 |
| auto[1] |
auto[0] |
auto[1] |
128938 |
1 |
|
|
T25 |
16 |
|
T1 |
962 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[0] |
883144 |
1 |
|
|
T25 |
531 |
|
T1 |
5487 |
|
T11 |
46 |
| auto[1] |
auto[1] |
auto[1] |
130966 |
1 |
|
|
T25 |
17 |
|
T1 |
1038 |
|
T11 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |