Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4231781 |
1 |
|
|
T25 |
992 |
|
T26 |
159 |
|
T1 |
15993 |
| auto[1] |
1998220 |
1 |
|
|
T25 |
1080 |
|
T1 |
10767 |
|
T11 |
223 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5972590 |
1 |
|
|
T25 |
2028 |
|
T26 |
159 |
|
T1 |
24851 |
| auto[1] |
257411 |
1 |
|
|
T25 |
44 |
|
T1 |
1909 |
|
T11 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4223457 |
1 |
|
|
T25 |
1003 |
|
T26 |
159 |
|
T1 |
14262 |
| auto[1] |
2006544 |
1 |
|
|
T25 |
1069 |
|
T1 |
12498 |
|
T11 |
153 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
879821 |
1 |
|
|
T25 |
482 |
|
T1 |
5437 |
|
T11 |
31 |
| auto[1] |
auto[0] |
auto[1] |
129838 |
1 |
|
|
T25 |
19 |
|
T1 |
981 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[0] |
869312 |
1 |
|
|
T25 |
543 |
|
T1 |
5152 |
|
T11 |
107 |
| auto[1] |
auto[1] |
auto[1] |
127573 |
1 |
|
|
T25 |
25 |
|
T1 |
928 |
|
T11 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |