Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4215778 |
1 |
|
|
T25 |
982 |
|
T26 |
159 |
|
T1 |
14280 |
| auto[1] |
2014223 |
1 |
|
|
T25 |
1090 |
|
T1 |
12480 |
|
T11 |
176 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5969782 |
1 |
|
|
T25 |
2026 |
|
T26 |
159 |
|
T1 |
24806 |
| auto[1] |
260219 |
1 |
|
|
T25 |
46 |
|
T1 |
1954 |
|
T11 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4205445 |
1 |
|
|
T25 |
842 |
|
T26 |
159 |
|
T1 |
14358 |
| auto[1] |
2024556 |
1 |
|
|
T25 |
1230 |
|
T1 |
12402 |
|
T11 |
197 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
885744 |
1 |
|
|
T25 |
542 |
|
T1 |
4865 |
|
T11 |
79 |
| auto[1] |
auto[0] |
auto[1] |
130552 |
1 |
|
|
T25 |
20 |
|
T1 |
904 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[0] |
878593 |
1 |
|
|
T25 |
642 |
|
T1 |
5583 |
|
T11 |
105 |
| auto[1] |
auto[1] |
auto[1] |
129667 |
1 |
|
|
T25 |
26 |
|
T1 |
1050 |
|
T11 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |