Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4207813 |
1 |
|
|
T25 |
999 |
|
T26 |
159 |
|
T1 |
15817 |
| auto[1] |
2022188 |
1 |
|
|
T25 |
1073 |
|
T1 |
10943 |
|
T11 |
122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5970479 |
1 |
|
|
T25 |
2045 |
|
T26 |
159 |
|
T1 |
24882 |
| auto[1] |
259522 |
1 |
|
|
T25 |
27 |
|
T1 |
1878 |
|
T11 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4206518 |
1 |
|
|
T25 |
1089 |
|
T26 |
159 |
|
T1 |
14580 |
| auto[1] |
2023483 |
1 |
|
|
T25 |
983 |
|
T1 |
12180 |
|
T11 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
885754 |
1 |
|
|
T25 |
425 |
|
T1 |
5549 |
|
T11 |
59 |
| auto[1] |
auto[0] |
auto[1] |
130769 |
1 |
|
|
T25 |
16 |
|
T1 |
1035 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[0] |
878207 |
1 |
|
|
T25 |
531 |
|
T1 |
4753 |
|
T11 |
49 |
| auto[1] |
auto[1] |
auto[1] |
128753 |
1 |
|
|
T25 |
11 |
|
T1 |
843 |
|
T11 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |