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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 936
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T77 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.655278863 Aug 16 05:00:46 PM PDT 24 Aug 16 05:00:46 PM PDT 24 31694665 ps
T763 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2984041611 Aug 16 05:00:47 PM PDT 24 Aug 16 05:00:48 PM PDT 24 57112868 ps
T764 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.650035932 Aug 16 05:01:09 PM PDT 24 Aug 16 05:01:10 PM PDT 24 50833283 ps
T765 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2095023583 Aug 16 05:01:04 PM PDT 24 Aug 16 05:01:05 PM PDT 24 138940988 ps
T766 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2722678284 Aug 16 05:00:47 PM PDT 24 Aug 16 05:00:50 PM PDT 24 266165279 ps
T767 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1891152718 Aug 16 05:01:09 PM PDT 24 Aug 16 05:01:10 PM PDT 24 12590546 ps
T768 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4163034279 Aug 16 05:01:37 PM PDT 24 Aug 16 05:01:38 PM PDT 24 60781050 ps
T769 /workspace/coverage/cover_reg_top/36.gpio_intr_test.99289405 Aug 16 05:01:24 PM PDT 24 Aug 16 05:01:25 PM PDT 24 15605333 ps
T41 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2373575652 Aug 16 05:01:01 PM PDT 24 Aug 16 05:01:03 PM PDT 24 154963271 ps
T770 /workspace/coverage/cover_reg_top/19.gpio_intr_test.44059937 Aug 16 05:01:24 PM PDT 24 Aug 16 05:01:25 PM PDT 24 17052763 ps
T771 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.437199160 Aug 16 05:01:09 PM PDT 24 Aug 16 05:01:10 PM PDT 24 184732985 ps
T772 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.557162462 Aug 16 05:01:01 PM PDT 24 Aug 16 05:01:01 PM PDT 24 15997405 ps
T773 /workspace/coverage/cover_reg_top/27.gpio_intr_test.414212802 Aug 16 05:01:22 PM PDT 24 Aug 16 05:01:23 PM PDT 24 11927844 ps
T774 /workspace/coverage/cover_reg_top/37.gpio_intr_test.649514388 Aug 16 05:01:28 PM PDT 24 Aug 16 05:01:29 PM PDT 24 124626327 ps
T775 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1597639230 Aug 16 05:01:08 PM PDT 24 Aug 16 05:01:09 PM PDT 24 41875535 ps
T78 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1581839543 Aug 16 05:01:09 PM PDT 24 Aug 16 05:01:09 PM PDT 24 13397500 ps
T776 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4003500106 Aug 16 05:01:25 PM PDT 24 Aug 16 05:01:26 PM PDT 24 15137103 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.232118018 Aug 16 05:01:08 PM PDT 24 Aug 16 05:01:09 PM PDT 24 20536270 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3021158518 Aug 16 05:01:03 PM PDT 24 Aug 16 05:01:04 PM PDT 24 86632294 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3748062183 Aug 16 05:01:15 PM PDT 24 Aug 16 05:01:17 PM PDT 24 137551808 ps
T780 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3044206134 Aug 16 05:00:48 PM PDT 24 Aug 16 05:00:50 PM PDT 24 37245105 ps
T79 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1695326810 Aug 16 05:00:53 PM PDT 24 Aug 16 05:00:54 PM PDT 24 31450305 ps
T781 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4248201911 Aug 16 05:01:17 PM PDT 24 Aug 16 05:01:20 PM PDT 24 138628718 ps
T782 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3467270986 Aug 16 05:01:24 PM PDT 24 Aug 16 05:01:25 PM PDT 24 49908887 ps
T37 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1594190492 Aug 16 05:01:08 PM PDT 24 Aug 16 05:01:09 PM PDT 24 169935100 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1545896516 Aug 16 05:01:05 PM PDT 24 Aug 16 05:01:05 PM PDT 24 15139334 ps
T784 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1881173356 Aug 16 05:01:11 PM PDT 24 Aug 16 05:01:11 PM PDT 24 23371129 ps
T80 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2922850211 Aug 16 05:00:47 PM PDT 24 Aug 16 05:00:48 PM PDT 24 36943808 ps
T785 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3774534597 Aug 16 05:00:53 PM PDT 24 Aug 16 05:00:54 PM PDT 24 226872959 ps
T786 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2526647421 Aug 16 05:01:00 PM PDT 24 Aug 16 05:01:02 PM PDT 24 126288037 ps
T787 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1087862262 Aug 16 05:01:08 PM PDT 24 Aug 16 05:01:09 PM PDT 24 34915754 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3214030214 Aug 16 05:00:55 PM PDT 24 Aug 16 05:00:57 PM PDT 24 232244438 ps
T789 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2365926733 Aug 16 05:01:01 PM PDT 24 Aug 16 05:01:02 PM PDT 24 80217404 ps
T790 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2247285880 Aug 16 05:01:06 PM PDT 24 Aug 16 05:01:08 PM PDT 24 173988837 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1556606512 Aug 16 05:00:48 PM PDT 24 Aug 16 05:00:52 PM PDT 24 1496408209 ps
T791 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3874882838 Aug 16 05:01:24 PM PDT 24 Aug 16 05:01:24 PM PDT 24 15363322 ps
T792 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3487079774 Aug 16 05:01:01 PM PDT 24 Aug 16 05:01:02 PM PDT 24 44281124 ps
T793 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2035737222 Aug 16 05:01:12 PM PDT 24 Aug 16 05:01:12 PM PDT 24 15364773 ps
T43 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3395124302 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:17 PM PDT 24 163662401 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3615156288 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:17 PM PDT 24 20843688 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1321373941 Aug 16 05:00:52 PM PDT 24 Aug 16 05:00:53 PM PDT 24 23057902 ps
T796 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.325722401 Aug 16 05:01:01 PM PDT 24 Aug 16 05:01:02 PM PDT 24 25975095 ps
T797 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3962845114 Aug 16 05:01:29 PM PDT 24 Aug 16 05:01:30 PM PDT 24 13481756 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1233193089 Aug 16 05:00:55 PM PDT 24 Aug 16 05:00:56 PM PDT 24 75192129 ps
T799 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.234482250 Aug 16 05:00:52 PM PDT 24 Aug 16 05:00:53 PM PDT 24 16426535 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.780404191 Aug 16 05:01:07 PM PDT 24 Aug 16 05:01:09 PM PDT 24 76762948 ps
T801 /workspace/coverage/cover_reg_top/46.gpio_intr_test.186036144 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 31863001 ps
T802 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3415718239 Aug 16 05:01:15 PM PDT 24 Aug 16 05:01:16 PM PDT 24 27056712 ps
T803 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3062783024 Aug 16 05:01:02 PM PDT 24 Aug 16 05:01:03 PM PDT 24 14354856 ps
T38 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.826694482 Aug 16 05:00:46 PM PDT 24 Aug 16 05:00:48 PM PDT 24 93531204 ps
T804 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3022853555 Aug 16 05:01:23 PM PDT 24 Aug 16 05:01:24 PM PDT 24 49629526 ps
T805 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3459756423 Aug 16 05:01:18 PM PDT 24 Aug 16 05:01:19 PM PDT 24 64148481 ps
T806 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2298030315 Aug 16 05:01:14 PM PDT 24 Aug 16 05:01:15 PM PDT 24 46288430 ps
T807 /workspace/coverage/cover_reg_top/15.gpio_intr_test.923825769 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:17 PM PDT 24 19011811 ps
T808 /workspace/coverage/cover_reg_top/33.gpio_intr_test.4169957970 Aug 16 05:01:23 PM PDT 24 Aug 16 05:01:24 PM PDT 24 11358595 ps
T809 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2020632051 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:16 PM PDT 24 14585875 ps
T810 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3908659835 Aug 16 05:01:07 PM PDT 24 Aug 16 05:01:08 PM PDT 24 18385972 ps
T811 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2964845922 Aug 16 05:01:10 PM PDT 24 Aug 16 05:01:11 PM PDT 24 27221717 ps
T812 /workspace/coverage/cover_reg_top/18.gpio_intr_test.626572630 Aug 16 05:01:18 PM PDT 24 Aug 16 05:01:19 PM PDT 24 110669216 ps
T813 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.93051460 Aug 16 05:00:56 PM PDT 24 Aug 16 05:00:56 PM PDT 24 61186457 ps
T814 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1427669468 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:18 PM PDT 24 33711582 ps
T815 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1402256604 Aug 16 05:00:47 PM PDT 24 Aug 16 05:00:48 PM PDT 24 106327972 ps
T816 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1794851617 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:19 PM PDT 24 365553010 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4192951902 Aug 16 05:00:54 PM PDT 24 Aug 16 05:00:55 PM PDT 24 22035352 ps
T818 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.570217363 Aug 16 05:00:54 PM PDT 24 Aug 16 05:00:55 PM PDT 24 22316654 ps
T819 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1198873580 Aug 16 05:01:22 PM PDT 24 Aug 16 05:01:23 PM PDT 24 63570186 ps
T820 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3428386067 Aug 16 05:01:22 PM PDT 24 Aug 16 05:01:23 PM PDT 24 17769189 ps
T821 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.429637508 Aug 16 05:01:00 PM PDT 24 Aug 16 05:01:01 PM PDT 24 148495373 ps
T82 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3514618123 Aug 16 05:00:49 PM PDT 24 Aug 16 05:00:50 PM PDT 24 99686324 ps
T822 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.599746186 Aug 16 05:01:09 PM PDT 24 Aug 16 05:01:10 PM PDT 24 48908077 ps
T823 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.666549384 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:18 PM PDT 24 62881232 ps
T824 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3871544617 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 25457750 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2810943255 Aug 16 05:01:18 PM PDT 24 Aug 16 05:01:18 PM PDT 24 17294960 ps
T826 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1867904515 Aug 16 05:01:15 PM PDT 24 Aug 16 05:01:18 PM PDT 24 97268455 ps
T39 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2162164655 Aug 16 05:01:20 PM PDT 24 Aug 16 05:01:22 PM PDT 24 64010264 ps
T827 /workspace/coverage/cover_reg_top/25.gpio_intr_test.4245586390 Aug 16 05:01:22 PM PDT 24 Aug 16 05:01:23 PM PDT 24 43667905 ps
T84 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2121304848 Aug 16 05:00:48 PM PDT 24 Aug 16 05:00:49 PM PDT 24 35278922 ps
T828 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2532404770 Aug 16 05:01:30 PM PDT 24 Aug 16 05:01:30 PM PDT 24 67917992 ps
T829 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3001202138 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:17 PM PDT 24 17084629 ps
T830 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4016918691 Aug 16 05:01:20 PM PDT 24 Aug 16 05:01:23 PM PDT 24 274280034 ps
T831 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1307097690 Aug 16 05:01:17 PM PDT 24 Aug 16 05:01:18 PM PDT 24 83061821 ps
T832 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2083167388 Aug 16 05:00:52 PM PDT 24 Aug 16 05:00:53 PM PDT 24 720959586 ps
T833 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4173015221 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:17 PM PDT 24 48089943 ps
T834 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.656817672 Aug 16 05:01:16 PM PDT 24 Aug 16 05:01:17 PM PDT 24 163750403 ps
T835 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2400558014 Aug 16 05:01:09 PM PDT 24 Aug 16 05:01:11 PM PDT 24 329821878 ps
T836 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.431889103 Aug 16 05:01:00 PM PDT 24 Aug 16 05:01:01 PM PDT 24 20321157 ps
T837 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1951220526 Aug 16 05:01:51 PM PDT 24 Aug 16 05:01:52 PM PDT 24 166606978 ps
T838 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.585744362 Aug 16 05:01:34 PM PDT 24 Aug 16 05:01:35 PM PDT 24 35191695 ps
T839 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1602355098 Aug 16 05:01:47 PM PDT 24 Aug 16 05:01:49 PM PDT 24 71930922 ps
T840 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3793952045 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:35 PM PDT 24 385372450 ps
T841 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2250498440 Aug 16 05:01:46 PM PDT 24 Aug 16 05:01:47 PM PDT 24 136235594 ps
T842 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11342284 Aug 16 05:01:29 PM PDT 24 Aug 16 05:01:31 PM PDT 24 185699591 ps
T843 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2033150683 Aug 16 05:01:41 PM PDT 24 Aug 16 05:01:43 PM PDT 24 41013972 ps
T844 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2232515271 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 464116868 ps
T845 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1808161809 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 169932967 ps
T846 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2167109421 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:46 PM PDT 24 142782788 ps
T847 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1474804146 Aug 16 05:01:43 PM PDT 24 Aug 16 05:01:45 PM PDT 24 328418025 ps
T848 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4191622948 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 58179978 ps
T849 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98034869 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:46 PM PDT 24 593671988 ps
T850 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2792417699 Aug 16 05:01:43 PM PDT 24 Aug 16 05:01:45 PM PDT 24 42494111 ps
T851 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.609540265 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 141251297 ps
T852 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1317002358 Aug 16 05:01:57 PM PDT 24 Aug 16 05:01:58 PM PDT 24 88580996 ps
T853 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.317020828 Aug 16 05:01:43 PM PDT 24 Aug 16 05:01:45 PM PDT 24 262614010 ps
T854 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2540769995 Aug 16 05:01:34 PM PDT 24 Aug 16 05:01:35 PM PDT 24 113411665 ps
T855 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3326469007 Aug 16 05:01:29 PM PDT 24 Aug 16 05:01:30 PM PDT 24 163432016 ps
T856 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.556976310 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 80118502 ps
T857 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.751372796 Aug 16 05:01:43 PM PDT 24 Aug 16 05:01:44 PM PDT 24 345522633 ps
T858 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3673411591 Aug 16 05:01:38 PM PDT 24 Aug 16 05:01:40 PM PDT 24 173199025 ps
T859 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4049217575 Aug 16 05:01:35 PM PDT 24 Aug 16 05:01:35 PM PDT 24 71338522 ps
T860 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.34634172 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:38 PM PDT 24 60812655 ps
T861 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2320149625 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:33 PM PDT 24 57146032 ps
T862 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4018724149 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 298022373 ps
T863 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.873092423 Aug 16 05:01:30 PM PDT 24 Aug 16 05:01:31 PM PDT 24 50199297 ps
T864 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1484621197 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:46 PM PDT 24 21213267 ps
T865 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.385593215 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 130538948 ps
T866 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1978909909 Aug 16 05:01:34 PM PDT 24 Aug 16 05:01:35 PM PDT 24 49795665 ps
T867 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.385795784 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:34 PM PDT 24 204196680 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.30069385 Aug 16 05:01:38 PM PDT 24 Aug 16 05:01:39 PM PDT 24 490121361 ps
T869 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101840289 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 203815611 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1365495027 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 51826459 ps
T871 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2327704554 Aug 16 05:01:37 PM PDT 24 Aug 16 05:01:38 PM PDT 24 43062882 ps
T872 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4129927860 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:46 PM PDT 24 66722611 ps
T873 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3252350311 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 67765012 ps
T874 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.273213748 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:47 PM PDT 24 215774329 ps
T875 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4178373525 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 94278548 ps
T876 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3503144470 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:34 PM PDT 24 43457661 ps
T877 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3726173933 Aug 16 05:01:34 PM PDT 24 Aug 16 05:01:35 PM PDT 24 23887742 ps
T878 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2905491743 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:34 PM PDT 24 159334196 ps
T879 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4135172535 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:33 PM PDT 24 191777957 ps
T880 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2064014110 Aug 16 05:01:40 PM PDT 24 Aug 16 05:01:41 PM PDT 24 161079552 ps
T881 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1332118231 Aug 16 05:01:43 PM PDT 24 Aug 16 05:01:44 PM PDT 24 42450218 ps
T882 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1227377427 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:46 PM PDT 24 70705406 ps
T883 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2843493384 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 313026951 ps
T884 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2054986099 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 121639789 ps
T885 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4107981363 Aug 16 05:01:48 PM PDT 24 Aug 16 05:01:49 PM PDT 24 20841207 ps
T886 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1066078465 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:33 PM PDT 24 243556169 ps
T887 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3159241200 Aug 16 05:01:49 PM PDT 24 Aug 16 05:01:50 PM PDT 24 79386219 ps
T888 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2969982684 Aug 16 05:01:46 PM PDT 24 Aug 16 05:01:47 PM PDT 24 137615114 ps
T889 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1204035879 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:34 PM PDT 24 37839232 ps
T890 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3139371489 Aug 16 05:01:48 PM PDT 24 Aug 16 05:01:50 PM PDT 24 70170201 ps
T891 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1524074509 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 101857381 ps
T892 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887133744 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 198160995 ps
T893 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4214842845 Aug 16 05:01:46 PM PDT 24 Aug 16 05:01:47 PM PDT 24 136261413 ps
T894 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4244777393 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 167769072 ps
T895 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1467896258 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 51683353 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2747111713 Aug 16 05:01:43 PM PDT 24 Aug 16 05:01:44 PM PDT 24 254562613 ps
T897 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.583583094 Aug 16 05:01:30 PM PDT 24 Aug 16 05:01:31 PM PDT 24 672755254 ps
T898 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1142247776 Aug 16 05:01:29 PM PDT 24 Aug 16 05:01:30 PM PDT 24 69967063 ps
T899 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3968382654 Aug 16 05:01:46 PM PDT 24 Aug 16 05:01:47 PM PDT 24 675352360 ps
T900 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136629353 Aug 16 05:01:29 PM PDT 24 Aug 16 05:01:30 PM PDT 24 170510951 ps
T901 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.703571805 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:34 PM PDT 24 73309609 ps
T902 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1048647647 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 41368585 ps
T903 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2764560942 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:46 PM PDT 24 47445438 ps
T904 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926061455 Aug 16 05:01:29 PM PDT 24 Aug 16 05:01:30 PM PDT 24 126609572 ps
T905 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2274710250 Aug 16 05:01:46 PM PDT 24 Aug 16 05:01:47 PM PDT 24 24539369 ps
T906 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1447788973 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 195913014 ps
T907 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1620284605 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:38 PM PDT 24 283924820 ps
T908 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3392335757 Aug 16 05:01:49 PM PDT 24 Aug 16 05:01:50 PM PDT 24 46660493 ps
T909 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.947645161 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 33448484 ps
T910 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3369484697 Aug 16 05:01:38 PM PDT 24 Aug 16 05:01:40 PM PDT 24 84707977 ps
T911 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3867514207 Aug 16 05:01:30 PM PDT 24 Aug 16 05:01:31 PM PDT 24 97886722 ps
T912 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2960031414 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:38 PM PDT 24 163473998 ps
T913 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3180896254 Aug 16 05:01:37 PM PDT 24 Aug 16 05:01:38 PM PDT 24 120511060 ps
T914 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1122038464 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:34 PM PDT 24 142592365 ps
T915 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1850901007 Aug 16 05:01:30 PM PDT 24 Aug 16 05:01:31 PM PDT 24 148869139 ps
T916 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.554319996 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:34 PM PDT 24 72481455 ps
T917 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1927000962 Aug 16 05:01:52 PM PDT 24 Aug 16 05:01:53 PM PDT 24 188567024 ps
T918 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3144683443 Aug 16 05:01:51 PM PDT 24 Aug 16 05:01:53 PM PDT 24 60843132 ps
T919 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211645391 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:46 PM PDT 24 141290019 ps
T920 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3490463624 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:38 PM PDT 24 30846087 ps
T921 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3031059742 Aug 16 05:01:28 PM PDT 24 Aug 16 05:01:29 PM PDT 24 114699258 ps
T922 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3296433818 Aug 16 05:01:28 PM PDT 24 Aug 16 05:01:29 PM PDT 24 327068428 ps
T923 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1957566813 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 46778101 ps
T924 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3425264397 Aug 16 05:01:44 PM PDT 24 Aug 16 05:01:45 PM PDT 24 50347768 ps
T925 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3389214780 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:37 PM PDT 24 78836941 ps
T926 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.557219668 Aug 16 05:01:35 PM PDT 24 Aug 16 05:01:36 PM PDT 24 38906087 ps
T927 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2852750789 Aug 16 05:01:33 PM PDT 24 Aug 16 05:01:34 PM PDT 24 227778690 ps
T928 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.919354864 Aug 16 05:01:31 PM PDT 24 Aug 16 05:01:32 PM PDT 24 38814881 ps
T929 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2519364408 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:33 PM PDT 24 241806536 ps
T930 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4258656160 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:37 PM PDT 24 82433831 ps
T931 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1244864780 Aug 16 05:01:36 PM PDT 24 Aug 16 05:01:37 PM PDT 24 564151532 ps
T932 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2659575961 Aug 16 05:01:51 PM PDT 24 Aug 16 05:01:53 PM PDT 24 73559557 ps
T933 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3501453714 Aug 16 05:01:45 PM PDT 24 Aug 16 05:01:47 PM PDT 24 117392232 ps
T934 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3562330593 Aug 16 05:01:32 PM PDT 24 Aug 16 05:01:34 PM PDT 24 50800322 ps
T935 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3001062173 Aug 16 05:01:34 PM PDT 24 Aug 16 05:01:35 PM PDT 24 105399976 ps
T936 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4164192012 Aug 16 05:01:39 PM PDT 24 Aug 16 05:01:40 PM PDT 24 27814903 ps

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1831749082
Short name T15
Test name
Test status
Simulation time 6482419880 ps
CPU time 219.1 seconds
Started Aug 16 05:11:05 PM PDT 24
Finished Aug 16 05:14:44 PM PDT 24
Peak memory 198512 kb
Host smart-85fb020c-628e-49ce-9a4f-4d7ccf3dc1aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1831749082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1831749082
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1053878649
Short name T12
Test name
Test status
Simulation time 160458959 ps
CPU time 2.2 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 198060 kb
Host smart-1f3363bd-412a-4fd6-9708-463889e95df5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053878649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1053878649
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.75617026
Short name T32
Test name
Test status
Simulation time 387214630 ps
CPU time 0.99 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:14 PM PDT 24
Peak memory 215148 kb
Host smart-c040306e-7103-418a-bd69-27fd958cb8bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75617026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.75617026
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1441187747
Short name T75
Test name
Test status
Simulation time 150411334 ps
CPU time 0.89 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 196656 kb
Host smart-f8a8ea58-5f92-4e11-a80b-1e870031f927
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441187747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1441187747
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1511398610
Short name T1
Test name
Test status
Simulation time 13741961489 ps
CPU time 39.81 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 198244 kb
Host smart-9515c737-396a-4a0b-86ad-c60297677805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511398610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1511398610
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3916119798
Short name T42
Test name
Test status
Simulation time 336146326 ps
CPU time 1.19 seconds
Started Aug 16 05:01:02 PM PDT 24
Finished Aug 16 05:01:04 PM PDT 24
Peak memory 198084 kb
Host smart-a58bb185-4d31-4871-9a74-941fc68753f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916119798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3916119798
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/15.gpio_alert_test.693554452
Short name T50
Test name
Test status
Simulation time 41312641 ps
CPU time 0.65 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 194212 kb
Host smart-f439418d-91bb-40d4-804c-33916e3095a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693554452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.693554452
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.370610429
Short name T66
Test name
Test status
Simulation time 136480065 ps
CPU time 0.89 seconds
Started Aug 16 05:00:49 PM PDT 24
Finished Aug 16 05:00:50 PM PDT 24
Peak memory 196800 kb
Host smart-fe70b461-0384-46b1-a4e2-e4ea5e9f8b90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370610429 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.370610429
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.826694482
Short name T38
Test name
Test status
Simulation time 93531204 ps
CPU time 1.16 seconds
Started Aug 16 05:00:46 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 198424 kb
Host smart-f35d719d-7005-4159-96b4-4a92c7325e24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826694482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.826694482
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3715659305
Short name T31
Test name
Test status
Simulation time 113657871 ps
CPU time 1.4 seconds
Started Aug 16 05:01:10 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 198512 kb
Host smart-046b53f5-4dc8-43e8-ab40-39659f1bcd1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715659305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3715659305
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.655278863
Short name T77
Test name
Test status
Simulation time 31694665 ps
CPU time 0.65 seconds
Started Aug 16 05:00:46 PM PDT 24
Finished Aug 16 05:00:46 PM PDT 24
Peak memory 195180 kb
Host smart-02ff8f74-5adf-4c9e-8e99-9a6c9791a2c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655278863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.655278863
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2722678284
Short name T766
Test name
Test status
Simulation time 266165279 ps
CPU time 3.28 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:50 PM PDT 24
Peak memory 198476 kb
Host smart-f05f4eb0-c612-407a-a19c-b17b2948cabe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722678284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2722678284
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2121304848
Short name T84
Test name
Test status
Simulation time 35278922 ps
CPU time 0.65 seconds
Started Aug 16 05:00:48 PM PDT 24
Finished Aug 16 05:00:49 PM PDT 24
Peak memory 195032 kb
Host smart-d5b58a0a-2756-48f8-85fe-95b437bf7cd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121304848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2121304848
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3044206134
Short name T780
Test name
Test status
Simulation time 37245105 ps
CPU time 1.23 seconds
Started Aug 16 05:00:48 PM PDT 24
Finished Aug 16 05:00:50 PM PDT 24
Peak memory 198548 kb
Host smart-d1876002-f13d-4b12-b1f5-3305bba0fd92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044206134 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3044206134
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.789865468
Short name T91
Test name
Test status
Simulation time 10864111 ps
CPU time 0.6 seconds
Started Aug 16 05:00:49 PM PDT 24
Finished Aug 16 05:00:50 PM PDT 24
Peak memory 194968 kb
Host smart-a9f0f98c-2919-422b-8962-ca68876e76f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789865468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.789865468
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3467453735
Short name T727
Test name
Test status
Simulation time 17230099 ps
CPU time 0.68 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 194820 kb
Host smart-50f9c2ce-8f54-41d1-a89a-f0aaaafd2e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467453735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3467453735
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1676080008
Short name T741
Test name
Test status
Simulation time 415522685 ps
CPU time 2.36 seconds
Started Aug 16 05:00:48 PM PDT 24
Finished Aug 16 05:00:50 PM PDT 24
Peak memory 198528 kb
Host smart-ca09e0e2-beea-474b-95de-d7aeaec355c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676080008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1676080008
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3514618123
Short name T82
Test name
Test status
Simulation time 99686324 ps
CPU time 0.85 seconds
Started Aug 16 05:00:49 PM PDT 24
Finished Aug 16 05:00:50 PM PDT 24
Peak memory 196460 kb
Host smart-230d4a21-d9c4-46da-9959-91a50bb0e30b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514618123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3514618123
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1556606512
Short name T81
Test name
Test status
Simulation time 1496408209 ps
CPU time 3.43 seconds
Started Aug 16 05:00:48 PM PDT 24
Finished Aug 16 05:00:52 PM PDT 24
Peak memory 197640 kb
Host smart-d19bdbf9-e5da-4a52-b027-4872f11b02b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556606512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1556606512
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2922850211
Short name T80
Test name
Test status
Simulation time 36943808 ps
CPU time 0.61 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 195512 kb
Host smart-9ef8a263-097e-476c-972b-c8d406a5eea2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922850211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2922850211
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.300087715
Short name T735
Test name
Test status
Simulation time 51102857 ps
CPU time 0.68 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 197416 kb
Host smart-c4567cf7-f78b-4222-a0a4-2821b3349fe0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300087715 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.300087715
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1694489037
Short name T725
Test name
Test status
Simulation time 12903384 ps
CPU time 0.65 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 194952 kb
Host smart-e3e1220f-6616-48de-ac93-a7e6cd29c544
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694489037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1694489037
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.694532138
Short name T745
Test name
Test status
Simulation time 15016888 ps
CPU time 0.66 seconds
Started Aug 16 05:00:48 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 194904 kb
Host smart-43d1912a-a2f3-48be-a3bd-808606bb2711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694532138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.694532138
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1402256604
Short name T815
Test name
Test status
Simulation time 106327972 ps
CPU time 0.86 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 196864 kb
Host smart-d498822b-bec6-4973-8f06-3865f22f6013
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402256604 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1402256604
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1073160619
Short name T711
Test name
Test status
Simulation time 233466276 ps
CPU time 1.26 seconds
Started Aug 16 05:00:46 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 198580 kb
Host smart-c00b6079-88c4-437e-93ac-248f9ebeb674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073160619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1073160619
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2984041611
Short name T763
Test name
Test status
Simulation time 57112868 ps
CPU time 0.91 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 197364 kb
Host smart-7c79f8a1-909e-4be7-b916-6ade9dfc4892
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984041611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2984041611
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1668852290
Short name T738
Test name
Test status
Simulation time 25231441 ps
CPU time 0.64 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 197496 kb
Host smart-bc049f97-de6e-4d0c-8be2-c4303f4a3340
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668852290 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1668852290
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1904753089
Short name T92
Test name
Test status
Simulation time 14801953 ps
CPU time 0.61 seconds
Started Aug 16 05:01:07 PM PDT 24
Finished Aug 16 05:01:08 PM PDT 24
Peak memory 195128 kb
Host smart-7e4795c8-f9d8-42c7-be5e-7db7c1db39d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904753089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1904753089
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3908659835
Short name T810
Test name
Test status
Simulation time 18385972 ps
CPU time 0.63 seconds
Started Aug 16 05:01:07 PM PDT 24
Finished Aug 16 05:01:08 PM PDT 24
Peak memory 194248 kb
Host smart-d7498c09-f85b-4997-b29f-3c11caf01362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908659835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3908659835
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.930666593
Short name T750
Test name
Test status
Simulation time 13082003 ps
CPU time 0.63 seconds
Started Aug 16 05:01:13 PM PDT 24
Finished Aug 16 05:01:14 PM PDT 24
Peak memory 195560 kb
Host smart-55a11baa-af4b-4748-bdde-28831f9cf9e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930666593 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.930666593
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3699158766
Short name T732
Test name
Test status
Simulation time 409235478 ps
CPU time 1.99 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 198576 kb
Host smart-2cb39059-bf69-4521-8d81-d26fee5d6980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699158766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3699158766
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.437199160
Short name T771
Test name
Test status
Simulation time 184732985 ps
CPU time 1.22 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 198616 kb
Host smart-4058ad66-fe2e-4ecd-9ff0-adec51ee7aa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437199160 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.437199160
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1581839543
Short name T78
Test name
Test status
Simulation time 13397500 ps
CPU time 0.63 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 195572 kb
Host smart-12b99e17-bbe7-416e-a23b-7bd03f1d6041
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581839543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1581839543
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1597639230
Short name T775
Test name
Test status
Simulation time 41875535 ps
CPU time 0.63 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 194236 kb
Host smart-8eb81942-67bc-47fc-88b7-649533f51cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597639230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1597639230
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4051124422
Short name T87
Test name
Test status
Simulation time 296591201 ps
CPU time 0.77 seconds
Started Aug 16 05:01:10 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 196348 kb
Host smart-174bee44-7a53-41c0-9960-39e021c58e67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051124422 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4051124422
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2425700927
Short name T740
Test name
Test status
Simulation time 79675708 ps
CPU time 2.13 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 198564 kb
Host smart-4cc1d8ee-545c-4635-9d53-bd9f268f1aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425700927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2425700927
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1594190492
Short name T37
Test name
Test status
Simulation time 169935100 ps
CPU time 0.9 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 197640 kb
Host smart-03d42075-d2aa-414f-a2c8-c8b9842d2a4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594190492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1594190492
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.987891550
Short name T762
Test name
Test status
Simulation time 70129319 ps
CPU time 0.72 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 197180 kb
Host smart-de3fa259-39bb-413c-9c04-e92ccc063c76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987891550 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.987891550
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1881173356
Short name T784
Test name
Test status
Simulation time 23371129 ps
CPU time 0.58 seconds
Started Aug 16 05:01:11 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 194428 kb
Host smart-191cfa78-d014-49ed-8763-95e60983733a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881173356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1881173356
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.665368049
Short name T742
Test name
Test status
Simulation time 191076497 ps
CPU time 0.61 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 194108 kb
Host smart-89b2fc1b-2b79-40f1-9842-5512111179ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665368049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.665368049
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.83146905
Short name T86
Test name
Test status
Simulation time 16742564 ps
CPU time 0.63 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:08 PM PDT 24
Peak memory 195236 kb
Host smart-2e0c8eb7-378d-4b81-bef0-eeb21418d848
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83146905 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.gpio_same_csr_outstanding.83146905
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3985918768
Short name T715
Test name
Test status
Simulation time 76004914 ps
CPU time 2.08 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 198540 kb
Host smart-d43faa43-359c-4264-8172-95ff57d07d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985918768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3985918768
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2400558014
Short name T835
Test name
Test status
Simulation time 329821878 ps
CPU time 1.42 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 198532 kb
Host smart-a90c9cc0-5ad2-41d9-949b-64306b37c5c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400558014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2400558014
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.780404191
Short name T800
Test name
Test status
Simulation time 76762948 ps
CPU time 1.03 seconds
Started Aug 16 05:01:07 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 198472 kb
Host smart-f14df0fb-65ab-41c9-9733-3e75e9236ab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780404191 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.780404191
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.232118018
Short name T777
Test name
Test status
Simulation time 20536270 ps
CPU time 0.59 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 194984 kb
Host smart-689cb9f5-dd31-4853-940a-f891260328fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232118018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.232118018
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.663476327
Short name T719
Test name
Test status
Simulation time 36724832 ps
CPU time 0.6 seconds
Started Aug 16 05:01:18 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 194024 kb
Host smart-609e58a5-f4b3-4116-b88e-14e41eaa2caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663476327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.663476327
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.650035932
Short name T764
Test name
Test status
Simulation time 50833283 ps
CPU time 0.76 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 196268 kb
Host smart-ff04ae87-a968-4db2-ba53-01a5904b9acb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650035932 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.650035932
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1794851617
Short name T816
Test name
Test status
Simulation time 365553010 ps
CPU time 2.73 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 198468 kb
Host smart-b741c544-9fc0-4a78-b053-8c4b8324639d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794851617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1794851617
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3278651410
Short name T29
Test name
Test status
Simulation time 227305630 ps
CPU time 1.52 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 198512 kb
Host smart-7a3c54ab-a306-4ea8-89b1-30a15da4a90f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278651410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3278651410
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3629373781
Short name T733
Test name
Test status
Simulation time 75535245 ps
CPU time 1.07 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198372 kb
Host smart-a55af502-c9a8-488b-b1a5-41d6eebfe5f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629373781 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3629373781
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2239577313
Short name T90
Test name
Test status
Simulation time 15211783 ps
CPU time 0.59 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 195596 kb
Host smart-e3b1cec2-8972-4f40-9c68-2ed64b330de3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239577313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2239577313
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3001202138
Short name T829
Test name
Test status
Simulation time 17084629 ps
CPU time 0.61 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 194264 kb
Host smart-5f803825-0fbd-4323-b6b6-65e0f725b74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001202138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3001202138
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.229708542
Short name T70
Test name
Test status
Simulation time 21903939 ps
CPU time 0.85 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 196660 kb
Host smart-d3abb3a6-8c40-46f9-b0a5-e25bc251252e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229708542 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.229708542
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2298030315
Short name T806
Test name
Test status
Simulation time 46288430 ps
CPU time 1.24 seconds
Started Aug 16 05:01:14 PM PDT 24
Finished Aug 16 05:01:15 PM PDT 24
Peak memory 198476 kb
Host smart-53608b83-51f0-42e3-b527-165078218256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298030315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2298030315
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3669857716
Short name T45
Test name
Test status
Simulation time 74091314 ps
CPU time 0.85 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 197356 kb
Host smart-d890ef0c-934a-491b-88f9-3e2dd615dd92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669857716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3669857716
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1393985351
Short name T755
Test name
Test status
Simulation time 40344750 ps
CPU time 0.92 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198416 kb
Host smart-ac8ad60b-c326-4a8b-a6c5-1e165ebb0efb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393985351 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1393985351
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4173015221
Short name T833
Test name
Test status
Simulation time 48089943 ps
CPU time 0.58 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 194916 kb
Host smart-7f582947-bf1e-4e00-bed7-15eafb313f8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173015221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4173015221
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.923825769
Short name T807
Test name
Test status
Simulation time 19011811 ps
CPU time 0.61 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 194236 kb
Host smart-d2c884b9-e206-4368-a41a-e3c320db3ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923825769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.923825769
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3415718239
Short name T802
Test name
Test status
Simulation time 27056712 ps
CPU time 0.76 seconds
Started Aug 16 05:01:15 PM PDT 24
Finished Aug 16 05:01:16 PM PDT 24
Peak memory 195356 kb
Host smart-34a1f52e-8558-4496-883a-6bf990ef8075
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415718239 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3415718239
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.666549384
Short name T823
Test name
Test status
Simulation time 62881232 ps
CPU time 1.3 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198496 kb
Host smart-88ac07c2-5103-46ec-91c7-86e38787baea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666549384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.666549384
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3395124302
Short name T43
Test name
Test status
Simulation time 163662401 ps
CPU time 0.87 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 198232 kb
Host smart-55f5111a-7b0e-4e71-b72b-eee45f88eec0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395124302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3395124302
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1427669468
Short name T814
Test name
Test status
Simulation time 33711582 ps
CPU time 1.67 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198708 kb
Host smart-4d3e3b53-f31f-48a4-b286-5b4460acb927
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427669468 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1427669468
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3762353942
Short name T736
Test name
Test status
Simulation time 20868133 ps
CPU time 0.62 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 195208 kb
Host smart-16c8b31b-bd8d-4dc2-8e73-a191fd3d7675
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762353942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3762353942
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.650046215
Short name T720
Test name
Test status
Simulation time 26629208 ps
CPU time 0.64 seconds
Started Aug 16 05:01:18 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 194860 kb
Host smart-32f6e617-0f38-4eea-aae0-f95fe0a0a92d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650046215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.650046215
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4163034279
Short name T768
Test name
Test status
Simulation time 60781050 ps
CPU time 0.74 seconds
Started Aug 16 05:01:37 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 196240 kb
Host smart-06afd86e-282a-4ea1-beb2-213f1545e4a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163034279 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4163034279
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1867904515
Short name T826
Test name
Test status
Simulation time 97268455 ps
CPU time 1.83 seconds
Started Aug 16 05:01:15 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198620 kb
Host smart-97914578-0e32-4fec-9a2e-47cf80772e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867904515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1867904515
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1307097690
Short name T831
Test name
Test status
Simulation time 83061821 ps
CPU time 1.15 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198528 kb
Host smart-470042a5-2b8b-41f1-a5ec-d2e24b88806d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307097690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1307097690
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.195028250
Short name T739
Test name
Test status
Simulation time 75597341 ps
CPU time 0.8 seconds
Started Aug 16 05:01:15 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 198368 kb
Host smart-84414a03-3b07-4f9f-9ef5-8afd42e2ae15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195028250 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.195028250
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2810943255
Short name T825
Test name
Test status
Simulation time 17294960 ps
CPU time 0.62 seconds
Started Aug 16 05:01:18 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 195644 kb
Host smart-2806c05b-271a-4246-b329-c7bfebbd3107
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810943255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2810943255
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3615156288
Short name T794
Test name
Test status
Simulation time 20843688 ps
CPU time 0.6 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 194856 kb
Host smart-78417032-a984-46b5-b641-de80c1c214a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615156288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3615156288
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3748062183
Short name T779
Test name
Test status
Simulation time 137551808 ps
CPU time 0.91 seconds
Started Aug 16 05:01:15 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 197408 kb
Host smart-360dbd1e-c625-4a10-90cd-fea5fe055138
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748062183 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3748062183
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4248201911
Short name T781
Test name
Test status
Simulation time 138628718 ps
CPU time 2.64 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:20 PM PDT 24
Peak memory 198596 kb
Host smart-7d6d305c-74e0-4f5f-87b0-94ab5373bf55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248201911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.4248201911
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.656817672
Short name T834
Test name
Test status
Simulation time 163750403 ps
CPU time 0.96 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:17 PM PDT 24
Peak memory 197520 kb
Host smart-8ba35e88-d656-461f-8c22-44216d557c6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656817672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.656817672
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3459756423
Short name T805
Test name
Test status
Simulation time 64148481 ps
CPU time 0.79 seconds
Started Aug 16 05:01:18 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 198188 kb
Host smart-f2200c75-49b3-4b40-b8dd-7648af8912c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459756423 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3459756423
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2020632051
Short name T809
Test name
Test status
Simulation time 14585875 ps
CPU time 0.58 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:16 PM PDT 24
Peak memory 193816 kb
Host smart-1124bfba-9165-4a6d-9d13-d73be9b30bef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020632051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2020632051
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.626572630
Short name T812
Test name
Test status
Simulation time 110669216 ps
CPU time 0.6 seconds
Started Aug 16 05:01:18 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 194824 kb
Host smart-7c2c16e4-af02-4166-9f72-b725e7ea1651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626572630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.626572630
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2117437141
Short name T67
Test name
Test status
Simulation time 123532651 ps
CPU time 0.82 seconds
Started Aug 16 05:01:15 PM PDT 24
Finished Aug 16 05:01:16 PM PDT 24
Peak memory 197444 kb
Host smart-2bb928fb-05e6-4197-bad6-a1f45b3f16e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117437141 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2117437141
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3799939183
Short name T728
Test name
Test status
Simulation time 67829189 ps
CPU time 1.86 seconds
Started Aug 16 05:01:16 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198544 kb
Host smart-7659bb15-8f7b-4076-9664-ddfcfbdd981d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799939183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3799939183
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.806773567
Short name T40
Test name
Test status
Simulation time 69480819 ps
CPU time 1.14 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 198500 kb
Host smart-f5c9fd9c-b79c-4bd7-9b58-afa1c180effe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806773567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.806773567
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1791958419
Short name T723
Test name
Test status
Simulation time 119079463 ps
CPU time 0.8 seconds
Started Aug 16 05:01:23 PM PDT 24
Finished Aug 16 05:01:24 PM PDT 24
Peak memory 198376 kb
Host smart-dd432d16-0666-4ecc-8939-76386bac03c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791958419 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1791958419
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.24068930
Short name T68
Test name
Test status
Simulation time 24199174 ps
CPU time 0.63 seconds
Started Aug 16 05:01:18 PM PDT 24
Finished Aug 16 05:01:19 PM PDT 24
Peak memory 195892 kb
Host smart-d44f2917-f7da-4a8d-804e-df12e6c53628
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_
csr_rw.24068930
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.44059937
Short name T770
Test name
Test status
Simulation time 17052763 ps
CPU time 0.64 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:25 PM PDT 24
Peak memory 194924 kb
Host smart-89495ca3-7e8f-4a5c-86f1-aa0af22cc624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44059937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.44059937
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4126853140
Short name T71
Test name
Test status
Simulation time 74400559 ps
CPU time 0.95 seconds
Started Aug 16 05:01:17 PM PDT 24
Finished Aug 16 05:01:18 PM PDT 24
Peak memory 197416 kb
Host smart-64c966fc-a112-4f24-8918-4979ad107c41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126853140 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.4126853140
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4016918691
Short name T830
Test name
Test status
Simulation time 274280034 ps
CPU time 2.82 seconds
Started Aug 16 05:01:20 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 198596 kb
Host smart-6bf22dd2-47d5-45c4-be0d-747b6505c314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016918691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.4016918691
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2162164655
Short name T39
Test name
Test status
Simulation time 64010264 ps
CPU time 1.14 seconds
Started Aug 16 05:01:20 PM PDT 24
Finished Aug 16 05:01:22 PM PDT 24
Peak memory 198496 kb
Host smart-0f8ee28c-dbed-44d0-82e1-01c0ed1ce921
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162164655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2162164655
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3214030214
Short name T788
Test name
Test status
Simulation time 232244438 ps
CPU time 2.23 seconds
Started Aug 16 05:00:55 PM PDT 24
Finished Aug 16 05:00:57 PM PDT 24
Peak memory 197512 kb
Host smart-0c9e55e8-89b3-4703-9fe6-b0fc324a7ac8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214030214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3214030214
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.93051460
Short name T813
Test name
Test status
Simulation time 61186457 ps
CPU time 0.66 seconds
Started Aug 16 05:00:56 PM PDT 24
Finished Aug 16 05:00:56 PM PDT 24
Peak memory 195088 kb
Host smart-c4f340eb-b3c8-42dd-b16f-5ef7aa6d34fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93051460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.93051460
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1321373941
Short name T795
Test name
Test status
Simulation time 23057902 ps
CPU time 0.77 seconds
Started Aug 16 05:00:52 PM PDT 24
Finished Aug 16 05:00:53 PM PDT 24
Peak memory 198372 kb
Host smart-92e75c4c-f9a1-49c6-a6d6-129726aa86a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321373941 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1321373941
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3101638808
Short name T73
Test name
Test status
Simulation time 21731123 ps
CPU time 0.63 seconds
Started Aug 16 05:00:46 PM PDT 24
Finished Aug 16 05:00:47 PM PDT 24
Peak memory 194980 kb
Host smart-293d1c5f-07cb-4e2e-9e20-571bbd7ca187
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101638808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3101638808
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1443233986
Short name T761
Test name
Test status
Simulation time 28948864 ps
CPU time 0.59 seconds
Started Aug 16 05:00:59 PM PDT 24
Finished Aug 16 05:01:00 PM PDT 24
Peak memory 194800 kb
Host smart-39112221-0afb-41ab-a51e-10d9bc175d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443233986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1443233986
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2925243458
Short name T760
Test name
Test status
Simulation time 468596197 ps
CPU time 0.94 seconds
Started Aug 16 05:00:47 PM PDT 24
Finished Aug 16 05:00:48 PM PDT 24
Peak memory 197616 kb
Host smart-d8af446b-d4d4-40f6-aea6-5a528e78b1e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925243458 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2925243458
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1233193089
Short name T798
Test name
Test status
Simulation time 75192129 ps
CPU time 1.56 seconds
Started Aug 16 05:00:55 PM PDT 24
Finished Aug 16 05:00:56 PM PDT 24
Peak memory 198564 kb
Host smart-fae64cf0-d1ea-4395-8ba4-34de4ab5ce77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233193089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1233193089
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2083167388
Short name T832
Test name
Test status
Simulation time 720959586 ps
CPU time 1.62 seconds
Started Aug 16 05:00:52 PM PDT 24
Finished Aug 16 05:00:53 PM PDT 24
Peak memory 198496 kb
Host smart-05b352e7-55bc-42cf-b105-42a58bbd4bc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083167388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2083167388
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3022853555
Short name T804
Test name
Test status
Simulation time 49629526 ps
CPU time 0.6 seconds
Started Aug 16 05:01:23 PM PDT 24
Finished Aug 16 05:01:24 PM PDT 24
Peak memory 194904 kb
Host smart-42122c31-7a6f-428f-bd2c-71bc6b84f06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022853555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3022853555
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3467270986
Short name T782
Test name
Test status
Simulation time 49908887 ps
CPU time 0.67 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:25 PM PDT 24
Peak memory 194296 kb
Host smart-4d32fcf9-aafa-4568-9dfd-d544b34b7136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467270986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3467270986
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3428386067
Short name T820
Test name
Test status
Simulation time 17769189 ps
CPU time 0.67 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194316 kb
Host smart-d6f5653f-9903-4542-88eb-de59e31fe7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428386067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3428386067
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1198873580
Short name T819
Test name
Test status
Simulation time 63570186 ps
CPU time 0.62 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194284 kb
Host smart-9a181d57-5272-4f5c-a8ab-cfafe33cad26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198873580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1198873580
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1788523764
Short name T749
Test name
Test status
Simulation time 78924776 ps
CPU time 0.61 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194308 kb
Host smart-4f239f1d-bc68-46c2-aa4a-5a7ca7b95a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788523764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1788523764
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.4245586390
Short name T827
Test name
Test status
Simulation time 43667905 ps
CPU time 0.6 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194924 kb
Host smart-17d236ad-1b67-48a2-90d8-b42af99ee235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245586390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.4245586390
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3486759274
Short name T758
Test name
Test status
Simulation time 14154236 ps
CPU time 0.6 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194304 kb
Host smart-61aab400-c67c-4a87-a9af-a4e53f5ec84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486759274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3486759274
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.414212802
Short name T773
Test name
Test status
Simulation time 11927844 ps
CPU time 0.56 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194164 kb
Host smart-9ee64cf2-3501-4e58-9c4a-90df1509f913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414212802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.414212802
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4096318918
Short name T752
Test name
Test status
Simulation time 23312989 ps
CPU time 0.59 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:23 PM PDT 24
Peak memory 194176 kb
Host smart-2734c8a9-0c9d-43be-91d1-b2a24c7fb78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096318918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4096318918
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4003500106
Short name T776
Test name
Test status
Simulation time 15137103 ps
CPU time 0.59 seconds
Started Aug 16 05:01:25 PM PDT 24
Finished Aug 16 05:01:26 PM PDT 24
Peak memory 194212 kb
Host smart-82d4b4e9-93bc-4606-9fc0-31193203a7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003500106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4003500106
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1695326810
Short name T79
Test name
Test status
Simulation time 31450305 ps
CPU time 0.77 seconds
Started Aug 16 05:00:53 PM PDT 24
Finished Aug 16 05:00:54 PM PDT 24
Peak memory 196912 kb
Host smart-5aa62e29-6884-4e12-a631-80169165cfbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695326810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1695326810
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.192358075
Short name T83
Test name
Test status
Simulation time 131218352 ps
CPU time 1.39 seconds
Started Aug 16 05:00:55 PM PDT 24
Finished Aug 16 05:00:56 PM PDT 24
Peak memory 197136 kb
Host smart-d034fafe-6733-4a97-8300-0511c03d11bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192358075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.192358075
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3464183428
Short name T76
Test name
Test status
Simulation time 17754296 ps
CPU time 0.69 seconds
Started Aug 16 05:00:59 PM PDT 24
Finished Aug 16 05:01:00 PM PDT 24
Peak memory 195932 kb
Host smart-a8234d84-4f00-4255-8761-db233bec60a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464183428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3464183428
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.936546528
Short name T729
Test name
Test status
Simulation time 97279456 ps
CPU time 0.92 seconds
Started Aug 16 05:00:59 PM PDT 24
Finished Aug 16 05:01:00 PM PDT 24
Peak memory 198324 kb
Host smart-6552d307-b70a-4ed2-a939-1abc2dc9c791
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936546528 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.936546528
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.234482250
Short name T799
Test name
Test status
Simulation time 16426535 ps
CPU time 0.67 seconds
Started Aug 16 05:00:52 PM PDT 24
Finished Aug 16 05:00:53 PM PDT 24
Peak memory 195960 kb
Host smart-3702aa2a-7225-4b14-8909-e6cb9e560232
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234482250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.234482250
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1611255407
Short name T748
Test name
Test status
Simulation time 31115292 ps
CPU time 0.61 seconds
Started Aug 16 05:00:54 PM PDT 24
Finished Aug 16 05:00:54 PM PDT 24
Peak memory 194236 kb
Host smart-409c2318-1969-41c9-a9fb-950597128578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611255407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1611255407
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3442403776
Short name T88
Test name
Test status
Simulation time 41396651 ps
CPU time 0.85 seconds
Started Aug 16 05:00:53 PM PDT 24
Finished Aug 16 05:00:54 PM PDT 24
Peak memory 196592 kb
Host smart-02abaf67-9448-4a27-b453-fc8bd9e9f6df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442403776 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3442403776
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.713847430
Short name T712
Test name
Test status
Simulation time 326018695 ps
CPU time 1.94 seconds
Started Aug 16 05:00:59 PM PDT 24
Finished Aug 16 05:01:01 PM PDT 24
Peak memory 198500 kb
Host smart-1314d287-9f43-400d-8a00-12a9c1a17570
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713847430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.713847430
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3774534597
Short name T785
Test name
Test status
Simulation time 226872959 ps
CPU time 0.88 seconds
Started Aug 16 05:00:53 PM PDT 24
Finished Aug 16 05:00:54 PM PDT 24
Peak memory 197448 kb
Host smart-21ae1a26-f63e-42d5-a607-68cc140dfd78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774534597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3774534597
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4050418220
Short name T737
Test name
Test status
Simulation time 22365717 ps
CPU time 0.59 seconds
Started Aug 16 05:01:22 PM PDT 24
Finished Aug 16 05:01:22 PM PDT 24
Peak memory 194120 kb
Host smart-e4d02954-cea5-4d05-88bd-603de2489b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050418220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4050418220
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3874882838
Short name T791
Test name
Test status
Simulation time 15363322 ps
CPU time 0.63 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:24 PM PDT 24
Peak memory 194232 kb
Host smart-e48750b3-f38e-4b4c-acb8-d90782257923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874882838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3874882838
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1627523942
Short name T753
Test name
Test status
Simulation time 24849781 ps
CPU time 0.59 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:25 PM PDT 24
Peak memory 194804 kb
Host smart-8b57c570-451d-413b-b2f7-f60bd2ea2c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627523942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1627523942
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4169957970
Short name T808
Test name
Test status
Simulation time 11358595 ps
CPU time 0.62 seconds
Started Aug 16 05:01:23 PM PDT 24
Finished Aug 16 05:01:24 PM PDT 24
Peak memory 194912 kb
Host smart-1aa7c720-384a-4e89-987d-701b5b9988d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169957970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4169957970
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.616587045
Short name T759
Test name
Test status
Simulation time 60179045 ps
CPU time 0.6 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:24 PM PDT 24
Peak memory 194220 kb
Host smart-6ff7b769-fb20-4b24-90b6-8d52c4445ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616587045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.616587045
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3073971638
Short name T746
Test name
Test status
Simulation time 13036620 ps
CPU time 0.59 seconds
Started Aug 16 05:01:21 PM PDT 24
Finished Aug 16 05:01:22 PM PDT 24
Peak memory 194220 kb
Host smart-f28109d5-cca9-4f2b-a809-e37639a3e0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073971638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3073971638
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.99289405
Short name T769
Test name
Test status
Simulation time 15605333 ps
CPU time 0.58 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:25 PM PDT 24
Peak memory 194856 kb
Host smart-69adbea7-cda9-48a7-8829-0bed581d6d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99289405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.99289405
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.649514388
Short name T774
Test name
Test status
Simulation time 124626327 ps
CPU time 0.61 seconds
Started Aug 16 05:01:28 PM PDT 24
Finished Aug 16 05:01:29 PM PDT 24
Peak memory 194280 kb
Host smart-b4d2dc06-2747-4a5a-b792-ee2de3ff5856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649514388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.649514388
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2245812875
Short name T731
Test name
Test status
Simulation time 13248732 ps
CPU time 0.58 seconds
Started Aug 16 05:01:24 PM PDT 24
Finished Aug 16 05:01:25 PM PDT 24
Peak memory 194856 kb
Host smart-1c3cb7cb-2a9f-4f35-bb48-94b17c82ed89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245812875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2245812875
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3363814675
Short name T730
Test name
Test status
Simulation time 167235530 ps
CPU time 0.63 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 194224 kb
Host smart-3b694927-7cd1-4ab0-aff8-6c2529520984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363814675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3363814675
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3111087638
Short name T72
Test name
Test status
Simulation time 53678764 ps
CPU time 0.81 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 196172 kb
Host smart-19aca320-e310-42d2-b799-120ee0d7006d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111087638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3111087638
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2095023583
Short name T765
Test name
Test status
Simulation time 138940988 ps
CPU time 1.48 seconds
Started Aug 16 05:01:04 PM PDT 24
Finished Aug 16 05:01:05 PM PDT 24
Peak memory 197352 kb
Host smart-f66b6f93-9f55-4b43-8af2-9bcf619ebc21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095023583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2095023583
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1178303423
Short name T734
Test name
Test status
Simulation time 22533829 ps
CPU time 0.62 seconds
Started Aug 16 05:01:03 PM PDT 24
Finished Aug 16 05:01:04 PM PDT 24
Peak memory 195108 kb
Host smart-1accb83e-0895-4908-a24c-36264116edfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178303423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1178303423
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2365926733
Short name T789
Test name
Test status
Simulation time 80217404 ps
CPU time 0.84 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 198388 kb
Host smart-713df3ab-ac80-4c6c-90ce-d0245e6cac7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365926733 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2365926733
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4192951902
Short name T817
Test name
Test status
Simulation time 22035352 ps
CPU time 0.62 seconds
Started Aug 16 05:00:54 PM PDT 24
Finished Aug 16 05:00:55 PM PDT 24
Peak memory 195116 kb
Host smart-4a7496ce-c0d0-4370-86bf-775a8c7b3a5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192951902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4192951902
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3487079774
Short name T792
Test name
Test status
Simulation time 44281124 ps
CPU time 0.59 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 194168 kb
Host smart-016e14f3-861b-4929-9604-bcbe68899b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487079774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3487079774
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.570217363
Short name T818
Test name
Test status
Simulation time 22316654 ps
CPU time 0.64 seconds
Started Aug 16 05:00:54 PM PDT 24
Finished Aug 16 05:00:55 PM PDT 24
Peak memory 194864 kb
Host smart-72050425-7ebe-4366-b991-6f39c7e2561a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570217363 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.570217363
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2061364681
Short name T717
Test name
Test status
Simulation time 23699715 ps
CPU time 1.31 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:03 PM PDT 24
Peak memory 198568 kb
Host smart-2ef6eeb2-a6eb-4858-af7f-4a2a9fc117cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061364681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2061364681
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1268175209
Short name T754
Test name
Test status
Simulation time 44664946 ps
CPU time 0.58 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 194148 kb
Host smart-1bb750f3-966e-433a-86f0-5abcff22bd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268175209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1268175209
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3871544617
Short name T824
Test name
Test status
Simulation time 25457750 ps
CPU time 0.61 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 194232 kb
Host smart-9a676a09-ac2f-4f55-8427-e9a8daf59c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871544617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3871544617
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.4202993719
Short name T743
Test name
Test status
Simulation time 14540880 ps
CPU time 0.63 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 194860 kb
Host smart-6cf11f14-61ca-44a3-9df3-10b46084f753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202993719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.4202993719
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1644297429
Short name T716
Test name
Test status
Simulation time 38892050 ps
CPU time 0.62 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 194240 kb
Host smart-9e66f8bf-be06-4aea-ae84-3df1150b22a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644297429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1644297429
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.120896467
Short name T722
Test name
Test status
Simulation time 13583016 ps
CPU time 0.58 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 194812 kb
Host smart-e16e56df-b66f-4c68-b641-4df8734c2685
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120896467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.120896467
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1083079212
Short name T724
Test name
Test status
Simulation time 46005588 ps
CPU time 0.58 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:29 PM PDT 24
Peak memory 194880 kb
Host smart-5712b097-e558-4d34-8f2e-5b83f20ecfef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083079212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1083079212
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.186036144
Short name T801
Test name
Test status
Simulation time 31863001 ps
CPU time 0.6 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 194852 kb
Host smart-2eed5daa-3a62-4800-9737-426ed7ca12b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186036144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.186036144
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2532404770
Short name T828
Test name
Test status
Simulation time 67917992 ps
CPU time 0.63 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 194260 kb
Host smart-7c1e5c0c-9b4e-4a59-9b27-f5cc1c3f30e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532404770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2532404770
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.753364942
Short name T718
Test name
Test status
Simulation time 71675743 ps
CPU time 0.59 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 194204 kb
Host smart-1b04d7e7-e1be-4b09-bc1e-9eb5caedf435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753364942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.753364942
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3962845114
Short name T797
Test name
Test status
Simulation time 13481756 ps
CPU time 0.58 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 194844 kb
Host smart-495f9966-e53c-4693-9f82-53ac34b86b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962845114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3962845114
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2321941112
Short name T756
Test name
Test status
Simulation time 17754778 ps
CPU time 0.88 seconds
Started Aug 16 05:01:03 PM PDT 24
Finished Aug 16 05:01:04 PM PDT 24
Peak memory 198392 kb
Host smart-fa7312eb-b164-4868-9656-10f097590832
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321941112 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2321941112
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.325722401
Short name T796
Test name
Test status
Simulation time 25975095 ps
CPU time 0.64 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 195188 kb
Host smart-67b06842-8e0f-473f-afa2-19aa7a8b46cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325722401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.325722401
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1545896516
Short name T783
Test name
Test status
Simulation time 15139334 ps
CPU time 0.58 seconds
Started Aug 16 05:01:05 PM PDT 24
Finished Aug 16 05:01:05 PM PDT 24
Peak memory 194144 kb
Host smart-ceaa7f2c-83f4-4282-862d-e730b2955372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545896516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1545896516
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.429637508
Short name T821
Test name
Test status
Simulation time 148495373 ps
CPU time 0.85 seconds
Started Aug 16 05:01:00 PM PDT 24
Finished Aug 16 05:01:01 PM PDT 24
Peak memory 197424 kb
Host smart-2ff5dab9-bd7c-4ff6-b811-03262ebc6fa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429637508 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.429637508
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3472396412
Short name T757
Test name
Test status
Simulation time 285156371 ps
CPU time 2.53 seconds
Started Aug 16 05:00:59 PM PDT 24
Finished Aug 16 05:01:01 PM PDT 24
Peak memory 198624 kb
Host smart-e60c3c86-d1b9-43ed-a1cb-16fd8a1de609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472396412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3472396412
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2373575652
Short name T41
Test name
Test status
Simulation time 154963271 ps
CPU time 1.16 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:03 PM PDT 24
Peak memory 198528 kb
Host smart-614be9e2-8ea7-458d-b635-28d7ef9f1f14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373575652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2373575652
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3163833415
Short name T751
Test name
Test status
Simulation time 50888874 ps
CPU time 1.29 seconds
Started Aug 16 05:01:02 PM PDT 24
Finished Aug 16 05:01:03 PM PDT 24
Peak memory 198632 kb
Host smart-80fdd88b-0887-4dd7-a66c-055118c172ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163833415 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3163833415
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.557162462
Short name T772
Test name
Test status
Simulation time 15997405 ps
CPU time 0.57 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:01 PM PDT 24
Peak memory 193764 kb
Host smart-0653cd03-e104-42b3-b367-90a773427180
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557162462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.557162462
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1854326932
Short name T744
Test name
Test status
Simulation time 17019560 ps
CPU time 0.64 seconds
Started Aug 16 05:01:04 PM PDT 24
Finished Aug 16 05:01:05 PM PDT 24
Peak memory 194272 kb
Host smart-28b8390d-75c5-4352-9c7f-ac39124db188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854326932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1854326932
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1419111555
Short name T89
Test name
Test status
Simulation time 54266257 ps
CPU time 0.71 seconds
Started Aug 16 05:01:02 PM PDT 24
Finished Aug 16 05:01:03 PM PDT 24
Peak memory 195088 kb
Host smart-6170740c-6ed4-45b8-a921-659c96d062c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419111555 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1419111555
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2526647421
Short name T786
Test name
Test status
Simulation time 126288037 ps
CPU time 1.79 seconds
Started Aug 16 05:01:00 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 198596 kb
Host smart-a22552e9-076d-452e-ac9c-f5bb9c2f895d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526647421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2526647421
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3021158518
Short name T778
Test name
Test status
Simulation time 86632294 ps
CPU time 1.23 seconds
Started Aug 16 05:01:03 PM PDT 24
Finished Aug 16 05:01:04 PM PDT 24
Peak memory 198496 kb
Host smart-712ea19e-e87a-42a1-b707-51f61a8dc897
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021158518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3021158518
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.431889103
Short name T836
Test name
Test status
Simulation time 20321157 ps
CPU time 0.87 seconds
Started Aug 16 05:01:00 PM PDT 24
Finished Aug 16 05:01:01 PM PDT 24
Peak memory 198316 kb
Host smart-9fd6145d-05bf-4125-bb42-ac41da2c1ee9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431889103 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.431889103
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3062783024
Short name T803
Test name
Test status
Simulation time 14354856 ps
CPU time 0.62 seconds
Started Aug 16 05:01:02 PM PDT 24
Finished Aug 16 05:01:03 PM PDT 24
Peak memory 195116 kb
Host smart-da550ce3-84b8-48f6-82d1-4db72b2695c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062783024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3062783024
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3755568928
Short name T721
Test name
Test status
Simulation time 22799102 ps
CPU time 0.62 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 194232 kb
Host smart-28b08f5e-219d-4f96-ac89-83ef940a0166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755568928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3755568928
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3213545498
Short name T69
Test name
Test status
Simulation time 35757725 ps
CPU time 0.83 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 196672 kb
Host smart-e7c051bc-87e1-4ffa-b78c-6003d5904d18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213545498 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3213545498
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2247285880
Short name T790
Test name
Test status
Simulation time 173988837 ps
CPU time 2.07 seconds
Started Aug 16 05:01:06 PM PDT 24
Finished Aug 16 05:01:08 PM PDT 24
Peak memory 198604 kb
Host smart-d44a6d83-e1c6-4cda-a537-80b5a3c66c71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247285880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2247285880
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.538487207
Short name T30
Test name
Test status
Simulation time 121671657 ps
CPU time 1.48 seconds
Started Aug 16 05:01:01 PM PDT 24
Finished Aug 16 05:01:02 PM PDT 24
Peak memory 198424 kb
Host smart-0c6b7120-b4cd-496a-9f10-e62ca3bff529
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538487207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.538487207
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3113120709
Short name T714
Test name
Test status
Simulation time 51164766 ps
CPU time 0.65 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 197284 kb
Host smart-4936cda0-c00c-4070-b649-a1a91b5e4dc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113120709 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3113120709
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3376463504
Short name T74
Test name
Test status
Simulation time 30728496 ps
CPU time 0.64 seconds
Started Aug 16 05:01:06 PM PDT 24
Finished Aug 16 05:01:07 PM PDT 24
Peak memory 195144 kb
Host smart-9b9f3451-8ced-4db9-bc96-b10c2c4b0623
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376463504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3376463504
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2611728521
Short name T726
Test name
Test status
Simulation time 15559628 ps
CPU time 0.63 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 194256 kb
Host smart-12524056-bdac-4147-b4f0-0c3b082dac3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611728521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2611728521
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1891152718
Short name T767
Test name
Test status
Simulation time 12590546 ps
CPU time 0.65 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 195060 kb
Host smart-6973b95a-1ddf-418f-a807-3a438abde779
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891152718 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1891152718
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2964845922
Short name T811
Test name
Test status
Simulation time 27221717 ps
CPU time 1.42 seconds
Started Aug 16 05:01:10 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 198536 kb
Host smart-c50d02e9-c594-4dc9-91c9-1315a470593b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964845922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2964845922
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.599746186
Short name T822
Test name
Test status
Simulation time 48908077 ps
CPU time 0.88 seconds
Started Aug 16 05:01:09 PM PDT 24
Finished Aug 16 05:01:10 PM PDT 24
Peak memory 197456 kb
Host smart-1b49d092-32fa-41a5-babb-03c3da17078a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599746186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.599746186
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.4291807597
Short name T747
Test name
Test status
Simulation time 38247952 ps
CPU time 0.78 seconds
Started Aug 16 05:01:13 PM PDT 24
Finished Aug 16 05:01:14 PM PDT 24
Peak memory 198392 kb
Host smart-896519e3-a63f-4d0c-945f-cfb85c8dec56
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291807597 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.4291807597
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2035737222
Short name T793
Test name
Test status
Simulation time 15364773 ps
CPU time 0.59 seconds
Started Aug 16 05:01:12 PM PDT 24
Finished Aug 16 05:01:12 PM PDT 24
Peak memory 195072 kb
Host smart-5495d914-5449-4de5-9f40-9dc0dd658fba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035737222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2035737222
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1087862262
Short name T787
Test name
Test status
Simulation time 34915754 ps
CPU time 0.62 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 194272 kb
Host smart-002b53a5-e596-4f9e-a5ed-a12609c8d6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087862262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1087862262
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.876632871
Short name T85
Test name
Test status
Simulation time 65008490 ps
CPU time 0.62 seconds
Started Aug 16 05:01:11 PM PDT 24
Finished Aug 16 05:01:11 PM PDT 24
Peak memory 195004 kb
Host smart-6b5e3e81-fab7-447c-a413-95b541287c49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876632871 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.876632871
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3825495582
Short name T713
Test name
Test status
Simulation time 73022455 ps
CPU time 1.97 seconds
Started Aug 16 05:01:11 PM PDT 24
Finished Aug 16 05:01:13 PM PDT 24
Peak memory 198492 kb
Host smart-bd6159d4-1ef9-4c66-9b81-67c1113bfbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825495582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3825495582
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.876175335
Short name T44
Test name
Test status
Simulation time 95852797 ps
CPU time 1.47 seconds
Started Aug 16 05:01:08 PM PDT 24
Finished Aug 16 05:01:09 PM PDT 24
Peak memory 198516 kb
Host smart-8cf811b0-c191-49d4-876f-49fdbebea050
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876175335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.876175335
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2081881461
Short name T665
Test name
Test status
Simulation time 37304266 ps
CPU time 0.65 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:24 PM PDT 24
Peak memory 194068 kb
Host smart-841900da-c3b3-4c66-ab5f-9c71c3dbb5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081881461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2081881461
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2316010801
Short name T696
Test name
Test status
Simulation time 34707556 ps
CPU time 0.8 seconds
Started Aug 16 05:10:09 PM PDT 24
Finished Aug 16 05:10:10 PM PDT 24
Peak memory 196004 kb
Host smart-4752a46b-bb69-4161-bf4d-73ee142eb7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316010801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2316010801
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3524315365
Short name T229
Test name
Test status
Simulation time 1114605981 ps
CPU time 15.91 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 196952 kb
Host smart-2bc410e8-4e0b-497e-a6c9-3b92671d5418
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524315365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3524315365
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.932071747
Short name T171
Test name
Test status
Simulation time 147637508 ps
CPU time 1 seconds
Started Aug 16 05:10:16 PM PDT 24
Finished Aug 16 05:10:17 PM PDT 24
Peak memory 198112 kb
Host smart-f624fe65-6c4a-4cf3-978d-3983d28524de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932071747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.932071747
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.457941914
Short name T577
Test name
Test status
Simulation time 96349783 ps
CPU time 0.88 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 196948 kb
Host smart-08b843c6-c892-4f7d-a963-986a80a77f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457941914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.457941914
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1038460393
Short name T710
Test name
Test status
Simulation time 88041581 ps
CPU time 1.69 seconds
Started Aug 16 05:10:10 PM PDT 24
Finished Aug 16 05:10:11 PM PDT 24
Peak memory 196468 kb
Host smart-1ac7e82d-6403-4e5e-b31d-da545174d7e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038460393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1038460393
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2231353567
Short name T220
Test name
Test status
Simulation time 233634453 ps
CPU time 2.71 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:27 PM PDT 24
Peak memory 198232 kb
Host smart-d805fd64-831a-4131-a8a5-02619ef270f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231353567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2231353567
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4058281085
Short name T580
Test name
Test status
Simulation time 128157598 ps
CPU time 1.25 seconds
Started Aug 16 05:10:30 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 197208 kb
Host smart-4aaec310-4d75-4c56-a8cf-92750e9d4855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058281085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4058281085
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2847675787
Short name T200
Test name
Test status
Simulation time 148142660 ps
CPU time 0.66 seconds
Started Aug 16 05:10:20 PM PDT 24
Finished Aug 16 05:10:20 PM PDT 24
Peak memory 195068 kb
Host smart-f335aced-9978-4108-ab4b-39c62187a1df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847675787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2847675787
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2556660897
Short name T669
Test name
Test status
Simulation time 659375253 ps
CPU time 4.38 seconds
Started Aug 16 05:10:17 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 198164 kb
Host smart-35282aa0-fc03-461a-b522-18be21551716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556660897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2556660897
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2619726261
Short name T47
Test name
Test status
Simulation time 131620850 ps
CPU time 0.78 seconds
Started Aug 16 05:10:15 PM PDT 24
Finished Aug 16 05:10:16 PM PDT 24
Peak memory 214876 kb
Host smart-2bc59378-2dfd-44ee-a6cc-b8b6349d13e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619726261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2619726261
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.4073060058
Short name T608
Test name
Test status
Simulation time 31442683 ps
CPU time 0.81 seconds
Started Aug 16 05:10:11 PM PDT 24
Finished Aug 16 05:10:12 PM PDT 24
Peak memory 195436 kb
Host smart-226825ca-3974-40ba-bea4-8d0322e47b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073060058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4073060058
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1909885367
Short name T441
Test name
Test status
Simulation time 81259284 ps
CPU time 0.88 seconds
Started Aug 16 05:10:04 PM PDT 24
Finished Aug 16 05:10:05 PM PDT 24
Peak memory 195484 kb
Host smart-d2f7697c-411b-4164-a6bf-9751401db7b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909885367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1909885367
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.65971317
Short name T4
Test name
Test status
Simulation time 11646954868 ps
CPU time 58.96 seconds
Started Aug 16 05:10:19 PM PDT 24
Finished Aug 16 05:11:18 PM PDT 24
Peak memory 198344 kb
Host smart-16410cdd-f8af-4835-880b-5db9d8f03e31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65971317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpi
o_stress_all.65971317
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.753896778
Short name T363
Test name
Test status
Simulation time 12152905 ps
CPU time 0.57 seconds
Started Aug 16 05:10:15 PM PDT 24
Finished Aug 16 05:10:16 PM PDT 24
Peak memory 194004 kb
Host smart-4ad2f185-1f01-4315-b6a9-5018dc5a0c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753896778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.753896778
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3663323638
Short name T432
Test name
Test status
Simulation time 26747645 ps
CPU time 0.76 seconds
Started Aug 16 05:10:14 PM PDT 24
Finished Aug 16 05:10:15 PM PDT 24
Peak memory 196016 kb
Host smart-f7616bc0-01a1-414f-9f8b-b3b3fceb23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663323638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3663323638
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1129820410
Short name T644
Test name
Test status
Simulation time 103817090 ps
CPU time 5.17 seconds
Started Aug 16 05:10:20 PM PDT 24
Finished Aug 16 05:10:25 PM PDT 24
Peak memory 198128 kb
Host smart-607f3ae3-e90b-48c9-a36b-2e3fdd504bef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129820410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1129820410
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3849834774
Short name T453
Test name
Test status
Simulation time 180125101 ps
CPU time 0.62 seconds
Started Aug 16 05:10:10 PM PDT 24
Finished Aug 16 05:10:11 PM PDT 24
Peak memory 194452 kb
Host smart-c431ae03-e84c-4496-a8f2-8ae303cef6d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849834774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3849834774
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1962403188
Short name T115
Test name
Test status
Simulation time 147832380 ps
CPU time 0.84 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:15 PM PDT 24
Peak memory 196276 kb
Host smart-56226226-d4f0-4ff3-9e2e-578604c84c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962403188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1962403188
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3515948631
Short name T629
Test name
Test status
Simulation time 41118296 ps
CPU time 1.77 seconds
Started Aug 16 05:10:12 PM PDT 24
Finished Aug 16 05:10:14 PM PDT 24
Peak memory 198168 kb
Host smart-5bb7e288-ad21-4ce7-8d41-642446d9f73b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515948631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3515948631
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.857831642
Short name T265
Test name
Test status
Simulation time 116652275 ps
CPU time 1.46 seconds
Started Aug 16 05:10:08 PM PDT 24
Finished Aug 16 05:10:10 PM PDT 24
Peak memory 195984 kb
Host smart-ad263d15-c844-429b-a50c-e5c258bbbc96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857831642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.857831642
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3174522245
Short name T516
Test name
Test status
Simulation time 76912460 ps
CPU time 0.71 seconds
Started Aug 16 05:10:19 PM PDT 24
Finished Aug 16 05:10:20 PM PDT 24
Peak memory 195448 kb
Host smart-78774bc7-b446-45c6-bdc1-7b8f34baf66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174522245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3174522245
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.4172106227
Short name T155
Test name
Test status
Simulation time 203651251 ps
CPU time 1.25 seconds
Started Aug 16 05:10:21 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 197156 kb
Host smart-cf7d1d65-2204-4cbc-a00e-46c430f3b509
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172106227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.4172106227
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.146423253
Short name T677
Test name
Test status
Simulation time 331391445 ps
CPU time 5.92 seconds
Started Aug 16 05:10:09 PM PDT 24
Finished Aug 16 05:10:16 PM PDT 24
Peak memory 198140 kb
Host smart-c75f9f8a-1f16-45ba-91c6-83852819fdda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146423253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.146423253
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.4273856660
Short name T316
Test name
Test status
Simulation time 284401192 ps
CPU time 0.72 seconds
Started Aug 16 05:10:12 PM PDT 24
Finished Aug 16 05:10:13 PM PDT 24
Peak memory 195180 kb
Host smart-1e6ee460-4135-48f0-9e26-b71bcc4756f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273856660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.4273856660
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1204321533
Short name T199
Test name
Test status
Simulation time 64684094 ps
CPU time 1.14 seconds
Started Aug 16 05:10:20 PM PDT 24
Finished Aug 16 05:10:21 PM PDT 24
Peak memory 196400 kb
Host smart-2e87492a-5417-40b1-b52e-57ca5b2f62b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204321533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1204321533
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3043793205
Short name T418
Test name
Test status
Simulation time 44906253888 ps
CPU time 83.67 seconds
Started Aug 16 05:10:10 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 198356 kb
Host smart-1617c640-028b-45e7-9dd4-7e3cf8b3ac52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043793205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3043793205
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1175981793
Short name T414
Test name
Test status
Simulation time 19276146 ps
CPU time 0.57 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:37 PM PDT 24
Peak memory 194736 kb
Host smart-a5135337-a1c7-4527-845b-787d5e5cc284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175981793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1175981793
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1806503896
Short name T643
Test name
Test status
Simulation time 38359462 ps
CPU time 0.81 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 196352 kb
Host smart-8be80584-b88d-4c72-8368-703c66c012a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806503896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1806503896
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1689282156
Short name T410
Test name
Test status
Simulation time 190541984 ps
CPU time 9.52 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 196928 kb
Host smart-da15f593-df66-4892-8db5-03575908a771
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689282156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1689282156
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3670759857
Short name T20
Test name
Test status
Simulation time 48686598 ps
CPU time 0.78 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 195952 kb
Host smart-0f179019-5956-4c62-abcc-2774e577770c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670759857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3670759857
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.992230709
Short name T692
Test name
Test status
Simulation time 32295414 ps
CPU time 1.01 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 196688 kb
Host smart-e64fb819-28bb-4d32-b954-53f35fef83cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992230709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.992230709
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2433404083
Short name T243
Test name
Test status
Simulation time 30332277 ps
CPU time 1.32 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 198240 kb
Host smart-f4692b0e-b99e-4159-adb9-5162d94b4052
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433404083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2433404083
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3939103584
Short name T190
Test name
Test status
Simulation time 108196301 ps
CPU time 1.01 seconds
Started Aug 16 05:10:39 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 196464 kb
Host smart-d116b453-0886-4bb3-ba77-010adbc787d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939103584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3939103584
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1842380968
Short name T146
Test name
Test status
Simulation time 168949932 ps
CPU time 0.9 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196708 kb
Host smart-d9487d34-af9d-4b5e-b595-f6c1cb1944b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842380968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1842380968
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3718000492
Short name T627
Test name
Test status
Simulation time 162041482 ps
CPU time 1.18 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 197196 kb
Host smart-159a271a-4dfd-4ea9-946d-367ffaa2be92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718000492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3718000492
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2829797913
Short name T377
Test name
Test status
Simulation time 472277549 ps
CPU time 5.24 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:10:55 PM PDT 24
Peak memory 198132 kb
Host smart-66b0b447-2aee-40eb-85e5-de57cabaf637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829797913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2829797913
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1720589094
Short name T201
Test name
Test status
Simulation time 256466542 ps
CPU time 1.1 seconds
Started Aug 16 05:10:38 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 195708 kb
Host smart-746a19ba-2bee-4a06-be86-20cf69b4bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720589094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1720589094
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.670886664
Short name T544
Test name
Test status
Simulation time 34969966 ps
CPU time 1.06 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 195624 kb
Host smart-c4be4d6f-ad2c-474f-b1e5-fa36a61f53f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670886664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.670886664
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.878079003
Short name T533
Test name
Test status
Simulation time 71139868023 ps
CPU time 178.7 seconds
Started Aug 16 05:10:39 PM PDT 24
Finished Aug 16 05:13:37 PM PDT 24
Peak memory 198332 kb
Host smart-68804a08-e483-42ea-ba8f-a068c2ff2747
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878079003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.878079003
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2339339601
Short name T607
Test name
Test status
Simulation time 34709375 ps
CPU time 0.54 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:42 PM PDT 24
Peak memory 192852 kb
Host smart-83e90940-7cd2-43c5-bdb3-341f7bd24e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339339601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2339339601
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2156752604
Short name T522
Test name
Test status
Simulation time 34384668 ps
CPU time 0.86 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 195552 kb
Host smart-37560df9-a1ff-403f-a5f9-589e0554d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156752604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2156752604
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3879743088
Short name T640
Test name
Test status
Simulation time 513885049 ps
CPU time 15.16 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 198120 kb
Host smart-f5b1d8da-b5ae-481d-8872-b97fd8f52245
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879743088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3879743088
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1281752144
Short name T660
Test name
Test status
Simulation time 25164089 ps
CPU time 0.66 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 195344 kb
Host smart-552e4d40-b450-428a-aaa5-ce203c523041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281752144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1281752144
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.4040336695
Short name T536
Test name
Test status
Simulation time 439931600 ps
CPU time 1.41 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 197156 kb
Host smart-0e206a8f-4d9e-4e2a-986a-794f82902d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040336695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.4040336695
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.427373053
Short name T705
Test name
Test status
Simulation time 76862246 ps
CPU time 2.93 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 198192 kb
Host smart-e16350d6-8ff3-48e1-920e-b931ab23432b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427373053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.427373053
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3968165622
Short name T64
Test name
Test status
Simulation time 200860173 ps
CPU time 2.33 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:39 PM PDT 24
Peak memory 198204 kb
Host smart-7d0c891c-5e81-460d-ae40-d55c81d29feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968165622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3968165622
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.827096155
Short name T599
Test name
Test status
Simulation time 80579215 ps
CPU time 1.02 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196812 kb
Host smart-2f3619fc-f44e-45c2-99b4-cad34983e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827096155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.827096155
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.179961579
Short name T18
Test name
Test status
Simulation time 35397991 ps
CPU time 1.24 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 197080 kb
Host smart-70618fe0-dc46-4cce-a723-67de86562d3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179961579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.179961579
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1472868168
Short name T2
Test name
Test status
Simulation time 390175372 ps
CPU time 1.47 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 198068 kb
Host smart-89d85e8a-42b9-4a16-900f-5e80ca7c42d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472868168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1472868168
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2142284123
Short name T641
Test name
Test status
Simulation time 654642779 ps
CPU time 1.08 seconds
Started Aug 16 05:10:39 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 195772 kb
Host smart-ea6f36ed-8224-4f9b-b1e3-dddc29783f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142284123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2142284123
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1562029461
Short name T179
Test name
Test status
Simulation time 46749482 ps
CPU time 0.94 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196088 kb
Host smart-a3c21342-c74f-4dca-ac80-92ecb24e4114
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562029461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1562029461
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1001945990
Short name T458
Test name
Test status
Simulation time 10660676249 ps
CPU time 110.21 seconds
Started Aug 16 05:10:30 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 198308 kb
Host smart-2ffacf14-f1f1-4b52-80ce-65b03b3b7429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001945990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1001945990
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.772458442
Short name T446
Test name
Test status
Simulation time 33887482 ps
CPU time 0.55 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 194108 kb
Host smart-3ec3584f-9875-4aa7-a633-2076adfa77a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772458442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.772458442
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2332068459
Short name T679
Test name
Test status
Simulation time 287750157 ps
CPU time 0.86 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 196600 kb
Host smart-77c125ff-b67d-45c2-a4ed-d712aa0442ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332068459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2332068459
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1695188480
Short name T559
Test name
Test status
Simulation time 517711231 ps
CPU time 4.04 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 196636 kb
Host smart-5463b60d-e1f8-4076-a284-f920c63bb536
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695188480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1695188480
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2008422218
Short name T7
Test name
Test status
Simulation time 219002331 ps
CPU time 0.8 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 196216 kb
Host smart-95da9be7-e4b5-440b-aa47-300aed4c5a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008422218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2008422218
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3293710444
Short name T575
Test name
Test status
Simulation time 533772036 ps
CPU time 1.21 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 198156 kb
Host smart-21caf17a-43b2-48c5-9556-32f760eae513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293710444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3293710444
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1207073360
Short name T443
Test name
Test status
Simulation time 70147064 ps
CPU time 2.72 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 196616 kb
Host smart-e789293f-9693-40a1-a71d-254d18f7d731
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207073360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1207073360
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1970109648
Short name T611
Test name
Test status
Simulation time 146612973 ps
CPU time 2.91 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 196676 kb
Host smart-8952795e-a9d1-44f0-b0d5-7462e86a3178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970109648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1970109648
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.670244478
Short name T698
Test name
Test status
Simulation time 65835582 ps
CPU time 1.03 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 196108 kb
Host smart-8d3dee8d-9350-4481-a6de-695b50bd8e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670244478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.670244478
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3107581015
Short name T668
Test name
Test status
Simulation time 51665700 ps
CPU time 1.16 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196192 kb
Host smart-9efac558-0a2d-4366-90ae-6e03bb9c421e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107581015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3107581015
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1544248971
Short name T684
Test name
Test status
Simulation time 471248693 ps
CPU time 2.61 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:39 PM PDT 24
Peak memory 198028 kb
Host smart-bc2e0578-2740-4be9-8e28-4af6c2730fc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544248971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1544248971
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.320344240
Short name T610
Test name
Test status
Simulation time 240617412 ps
CPU time 0.78 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196108 kb
Host smart-4fab0461-a725-4219-8a24-c80ded1165dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320344240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.320344240
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2505121947
Short name T323
Test name
Test status
Simulation time 105915223 ps
CPU time 0.82 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 195948 kb
Host smart-3f172731-b2e3-4a2c-b28b-cdf5d4cc5c43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505121947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2505121947
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.302362270
Short name T570
Test name
Test status
Simulation time 57256747831 ps
CPU time 206.65 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:14:04 PM PDT 24
Peak memory 198348 kb
Host smart-250e1886-6b08-444e-a016-96c6869e1299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302362270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.302362270
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.199733089
Short name T457
Test name
Test status
Simulation time 44282239 ps
CPU time 0.57 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 194804 kb
Host smart-82061f67-18e1-4176-a1d7-c35ef9ef79ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199733089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.199733089
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2968458093
Short name T357
Test name
Test status
Simulation time 28101684 ps
CPU time 0.83 seconds
Started Aug 16 05:10:38 PM PDT 24
Finished Aug 16 05:10:39 PM PDT 24
Peak memory 196348 kb
Host smart-0a827572-f6b7-43ac-9e16-35ed49e2c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968458093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2968458093
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.181572644
Short name T428
Test name
Test status
Simulation time 5726239536 ps
CPU time 27.18 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:11:08 PM PDT 24
Peak memory 197048 kb
Host smart-279c2edc-101c-4671-b464-e77ae960fec5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181572644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.181572644
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3980070225
Short name T405
Test name
Test status
Simulation time 142003485 ps
CPU time 0.94 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 197224 kb
Host smart-618e45ed-a5a1-46da-817c-e9b765f2d465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980070225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3980070225
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1914230662
Short name T283
Test name
Test status
Simulation time 192155871 ps
CPU time 0.78 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 195452 kb
Host smart-9a57e95c-bc02-4a28-88cb-8a2ea91aacc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914230662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1914230662
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.648413490
Short name T17
Test name
Test status
Simulation time 338250825 ps
CPU time 3.31 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 198228 kb
Host smart-233c21b1-b5d1-4cd2-897d-8805b37c35ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648413490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.648413490
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3878158363
Short name T139
Test name
Test status
Simulation time 161901112 ps
CPU time 2.36 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 197280 kb
Host smart-d69aae73-7be6-415c-9749-9c0f765e9248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878158363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3878158363
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.428145837
Short name T383
Test name
Test status
Simulation time 130892532 ps
CPU time 0.92 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 196012 kb
Host smart-2143bca4-f24f-40be-b8a7-290ca35ce9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428145837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.428145837
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2036562850
Short name T160
Test name
Test status
Simulation time 98159897 ps
CPU time 0.82 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 196724 kb
Host smart-ba44f12c-8624-43f3-89f5-c2dac2302fc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036562850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2036562850
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1338184039
Short name T181
Test name
Test status
Simulation time 116894908 ps
CPU time 5.32 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:42 PM PDT 24
Peak memory 198128 kb
Host smart-b376633a-a1a5-4391-9e00-e0d41931c2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338184039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1338184039
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1295285941
Short name T272
Test name
Test status
Simulation time 143094110 ps
CPU time 0.88 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 195308 kb
Host smart-4923f3ba-803e-44db-ae3f-bda58e164dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295285941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1295285941
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.4196218682
Short name T178
Test name
Test status
Simulation time 113765161 ps
CPU time 1.17 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 195992 kb
Host smart-c582391a-3e3a-4b7d-8a8e-badc87470bab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196218682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.4196218682
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2264440143
Short name T534
Test name
Test status
Simulation time 31662535406 ps
CPU time 195.38 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:13:53 PM PDT 24
Peak memory 198332 kb
Host smart-1ad7a9f6-16d8-419d-afb6-2a9238edeee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264440143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2264440143
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1012490543
Short name T398
Test name
Test status
Simulation time 12190486 ps
CPU time 0.58 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 194028 kb
Host smart-fefb0d1c-d4db-4419-9383-16dd16a614ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012490543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1012490543
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3869811848
Short name T431
Test name
Test status
Simulation time 69260403 ps
CPU time 0.7 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:37 PM PDT 24
Peak memory 194240 kb
Host smart-c4d57188-7013-4a46-8123-eac50c97dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869811848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3869811848
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2883550693
Short name T422
Test name
Test status
Simulation time 1466833457 ps
CPU time 25.04 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:11:10 PM PDT 24
Peak memory 198164 kb
Host smart-f4ab6bb3-b654-45fa-95e2-3ea2d5a36090
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883550693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2883550693
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2003521976
Short name T382
Test name
Test status
Simulation time 298193110 ps
CPU time 1 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 197256 kb
Host smart-d7d2daad-4618-42f1-b2c3-8600de690562
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003521976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2003521976
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2988732497
Short name T150
Test name
Test status
Simulation time 78517907 ps
CPU time 0.93 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196156 kb
Host smart-46e77b66-8cf7-484d-88a3-160e0aa40aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988732497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2988732497
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3750227303
Short name T217
Test name
Test status
Simulation time 47864079 ps
CPU time 1.95 seconds
Started Aug 16 05:10:39 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 198208 kb
Host smart-77964395-4799-4150-86a8-666b7246872b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750227303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3750227303
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1484630834
Short name T406
Test name
Test status
Simulation time 376672104 ps
CPU time 1.53 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:37 PM PDT 24
Peak memory 196980 kb
Host smart-efe44f26-9a71-4d44-bbc2-029d0fe728d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484630834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1484630834
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.4091826959
Short name T501
Test name
Test status
Simulation time 25182131 ps
CPU time 0.67 seconds
Started Aug 16 05:10:58 PM PDT 24
Finished Aug 16 05:10:59 PM PDT 24
Peak memory 194424 kb
Host smart-8f45a431-63ac-4813-8f17-cfd777e5f8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091826959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.4091826959
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2664865915
Short name T542
Test name
Test status
Simulation time 57030911 ps
CPU time 1.05 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:42 PM PDT 24
Peak memory 196044 kb
Host smart-ebf6d9f3-0a50-474b-85cb-41ca6c89b808
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664865915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2664865915
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3272906876
Short name T704
Test name
Test status
Simulation time 655869930 ps
CPU time 3.04 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 198132 kb
Host smart-2c27e6dc-a798-417b-ac7c-2011fa5421e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272906876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3272906876
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3745502240
Short name T108
Test name
Test status
Simulation time 167325966 ps
CPU time 1.22 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196944 kb
Host smart-1213906a-66ea-4c28-a5cb-ba7db1271003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745502240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3745502240
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1441651108
Short name T427
Test name
Test status
Simulation time 41334767 ps
CPU time 0.94 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:39 PM PDT 24
Peak memory 196372 kb
Host smart-b8073e54-6fe1-4ca4-bee2-dbddfdfdc6d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441651108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1441651108
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.4246536134
Short name T652
Test name
Test status
Simulation time 13887649599 ps
CPU time 39.46 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:11:20 PM PDT 24
Peak memory 198260 kb
Host smart-f396a295-c4ec-4073-91ea-bbbf4544bff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246536134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.4246536134
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.695946555
Short name T708
Test name
Test status
Simulation time 133788677 ps
CPU time 0.85 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196096 kb
Host smart-1d5771c7-5bb8-41a4-83b4-6670bea1b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695946555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.695946555
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2339603620
Short name T681
Test name
Test status
Simulation time 188865842 ps
CPU time 6.59 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 196928 kb
Host smart-807534bc-cabf-45c8-a527-704a31263852
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339603620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2339603620
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.660763065
Short name T282
Test name
Test status
Simulation time 143560313 ps
CPU time 0.98 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 197968 kb
Host smart-1571fb66-8f30-424c-be64-9bdbb30bc3ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660763065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.660763065
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2364487006
Short name T197
Test name
Test status
Simulation time 70057654 ps
CPU time 1.06 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 196044 kb
Host smart-15534259-3c26-41b3-9d74-e5940b96eae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364487006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2364487006
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.30447959
Short name T539
Test name
Test status
Simulation time 55523403 ps
CPU time 2.31 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 198200 kb
Host smart-a34106a4-854a-4154-91fd-00f08f5842eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.gpio_intr_with_filter_rand_intr_event.30447959
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3992444520
Short name T686
Test name
Test status
Simulation time 62019357 ps
CPU time 1.87 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196156 kb
Host smart-7379f9f9-e02d-4fd2-8618-cbd0d7ca5b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992444520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3992444520
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3162456783
Short name T225
Test name
Test status
Simulation time 15988981 ps
CPU time 0.68 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 194368 kb
Host smart-8cf25b47-caf5-434e-8d89-52af98fc262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162456783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3162456783
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3817988105
Short name T216
Test name
Test status
Simulation time 46000321 ps
CPU time 0.76 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 196120 kb
Host smart-f0ab75a1-c8d1-4d58-bb76-0ee75da4d0f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817988105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3817988105
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3593590538
Short name T129
Test name
Test status
Simulation time 115332171 ps
CPU time 2.44 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 198108 kb
Host smart-71425c93-47e0-445e-b80f-316bbdeab6e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593590538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3593590538
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2709191929
Short name T573
Test name
Test status
Simulation time 37189604 ps
CPU time 1.02 seconds
Started Aug 16 05:10:42 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 195644 kb
Host smart-18f27903-ddde-4969-bcac-d24ede3dddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709191929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2709191929
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1970007408
Short name T413
Test name
Test status
Simulation time 81441913 ps
CPU time 1.16 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 197064 kb
Host smart-a8aa8035-df93-4bff-9dbe-7e4411da9742
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970007408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1970007408
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3311086327
Short name T8
Test name
Test status
Simulation time 167555735686 ps
CPU time 140.99 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:13:06 PM PDT 24
Peak memory 191972 kb
Host smart-7dbabf9e-e55f-4eb2-b317-e72c82d30094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311086327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3311086327
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1829785957
Short name T121
Test name
Test status
Simulation time 43065676 ps
CPU time 0.57 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 194048 kb
Host smart-cf7ae874-d608-4d26-a490-e57f9995b390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829785957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1829785957
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2254634042
Short name T571
Test name
Test status
Simulation time 53672869 ps
CPU time 0.93 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 196588 kb
Host smart-c6c48ee9-9e83-4f12-8246-1fcff06a39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254634042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2254634042
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1947851879
Short name T636
Test name
Test status
Simulation time 1767481220 ps
CPU time 12.59 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 197172 kb
Host smart-f1760379-dc62-4094-ad88-c67d90d325eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947851879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1947851879
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3318392167
Short name T461
Test name
Test status
Simulation time 61213507 ps
CPU time 0.92 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:54 PM PDT 24
Peak memory 196496 kb
Host smart-c74148d5-3cdc-43a9-96b6-ab066576f963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318392167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3318392167
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2050449184
Short name T266
Test name
Test status
Simulation time 249590934 ps
CPU time 1.24 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 196032 kb
Host smart-4e4b6044-6096-40c4-b4e4-baca7143e230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050449184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2050449184
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2932792981
Short name T568
Test name
Test status
Simulation time 81101188 ps
CPU time 3.24 seconds
Started Aug 16 05:10:38 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 198068 kb
Host smart-643c231f-85dd-4cfe-9cdd-59fa1988a49b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932792981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2932792981
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.365285656
Short name T262
Test name
Test status
Simulation time 202849775 ps
CPU time 2.09 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 197068 kb
Host smart-2de9c0e2-048e-4d6c-ac24-d5adbdc23ea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365285656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
365285656
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3925947866
Short name T638
Test name
Test status
Simulation time 219947009 ps
CPU time 1.26 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 196728 kb
Host smart-d286360d-30a8-4495-8761-31152849fb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925947866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3925947866
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3065800931
Short name T173
Test name
Test status
Simulation time 46527516 ps
CPU time 1.04 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196144 kb
Host smart-d526965a-9203-4190-8fcd-1f6c706bf040
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065800931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3065800931
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1581616641
Short name T678
Test name
Test status
Simulation time 135652273 ps
CPU time 2.51 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:37 PM PDT 24
Peak memory 198120 kb
Host smart-3648aef7-c1b8-4458-a314-0d7660a1e668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581616641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1581616641
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4068993647
Short name T393
Test name
Test status
Simulation time 134131112 ps
CPU time 1.14 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 195788 kb
Host smart-15705c4a-1ae9-4557-865e-b34779cb7e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068993647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4068993647
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1155570732
Short name T594
Test name
Test status
Simulation time 125793872 ps
CPU time 0.85 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196180 kb
Host smart-50a19f46-2d0c-4aef-8ade-ee34bd099c95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155570732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1155570732
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.4047850366
Short name T540
Test name
Test status
Simulation time 5495889611 ps
CPU time 60.4 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:11:44 PM PDT 24
Peak memory 198352 kb
Host smart-6c82ba53-e152-4505-8c15-9cf547defb93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047850366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.4047850366
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.4136930986
Short name T622
Test name
Test status
Simulation time 19313017 ps
CPU time 0.55 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 194720 kb
Host smart-d216ce2d-85ab-42aa-93f9-d2efa2b6527a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136930986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.4136930986
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3334419845
Short name T387
Test name
Test status
Simulation time 24137974 ps
CPU time 0.73 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196112 kb
Host smart-cc2c61ca-4a04-44d4-b9d6-c9e6f64c55a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334419845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3334419845
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.513023139
Short name T308
Test name
Test status
Simulation time 427298828 ps
CPU time 14.27 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196976 kb
Host smart-2a65d6cc-15d4-4945-82ed-cd394eb5da1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513023139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.513023139
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2565659631
Short name T299
Test name
Test status
Simulation time 35836127 ps
CPU time 0.71 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 194740 kb
Host smart-06678897-27f4-40b5-b3f8-53736204b2ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565659631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2565659631
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2019400123
Short name T613
Test name
Test status
Simulation time 158357337 ps
CPU time 1.1 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196704 kb
Host smart-5cfe35a2-4aab-47ee-b823-13455f82f894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019400123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2019400123
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1964582246
Short name T462
Test name
Test status
Simulation time 201668439 ps
CPU time 2.25 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 198104 kb
Host smart-034d815a-1ac3-4d3c-b01c-ae46eae38123
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964582246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1964582246
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3628875120
Short name T655
Test name
Test status
Simulation time 105616930 ps
CPU time 2.96 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 197168 kb
Host smart-bb81637e-8eb9-4b14-97c1-3883ad55a3d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628875120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3628875120
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4197284839
Short name T492
Test name
Test status
Simulation time 23980270 ps
CPU time 0.83 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 196516 kb
Host smart-a1812675-e48f-4b91-8cae-8e503cd6ad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197284839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4197284839
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2948174604
Short name T291
Test name
Test status
Simulation time 18860143 ps
CPU time 0.7 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 194420 kb
Host smart-06f514d5-1793-4c06-99ac-f245a89aa6a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948174604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2948174604
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3252360734
Short name T653
Test name
Test status
Simulation time 117921187 ps
CPU time 1.51 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 198152 kb
Host smart-b3c762a0-7688-49b5-885f-d268b9ccd514
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252360734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3252360734
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.908094608
Short name T180
Test name
Test status
Simulation time 352862140 ps
CPU time 1.01 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 195896 kb
Host smart-c3237915-445a-4f77-ad7e-472e1d9e25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908094608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.908094608
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3374197761
Short name T518
Test name
Test status
Simulation time 90134047 ps
CPU time 1.01 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 195880 kb
Host smart-a74d3861-7a2c-4c13-947e-3daa6425050f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374197761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3374197761
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3692262576
Short name T138
Test name
Test status
Simulation time 18581699866 ps
CPU time 123.95 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:12:47 PM PDT 24
Peak memory 198328 kb
Host smart-8c2d33af-fe1a-409d-8ccd-4074bf3a2f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692262576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3692262576
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3261038615
Short name T517
Test name
Test status
Simulation time 153098435 ps
CPU time 0.58 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 194760 kb
Host smart-6b180578-c168-4438-9c76-4d85046e1db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261038615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3261038615
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.4266735306
Short name T128
Test name
Test status
Simulation time 20489935 ps
CPU time 0.65 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 194956 kb
Host smart-8004be7c-cf69-4dc2-9128-c05dd7357afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266735306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4266735306
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3243449058
Short name T158
Test name
Test status
Simulation time 445961839 ps
CPU time 20.71 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:11:06 PM PDT 24
Peak memory 197372 kb
Host smart-021c9bc9-883e-4da9-90b7-c52207d8fa75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243449058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3243449058
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3648909177
Short name T188
Test name
Test status
Simulation time 88561210 ps
CPU time 0.88 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196024 kb
Host smart-7283ff54-c6e5-467b-b034-33bddae25927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648909177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3648909177
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.560549378
Short name T355
Test name
Test status
Simulation time 73210283 ps
CPU time 1.12 seconds
Started Aug 16 05:11:09 PM PDT 24
Finished Aug 16 05:11:10 PM PDT 24
Peak memory 196276 kb
Host smart-94d6d234-d11c-4aa0-8313-39a4640ac863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560549378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.560549378
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3887789338
Short name T612
Test name
Test status
Simulation time 83436381 ps
CPU time 1 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 196068 kb
Host smart-bf6fbc29-b8db-41c7-aad1-f53b5fe714f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887789338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3887789338
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2750710948
Short name T109
Test name
Test status
Simulation time 124437420 ps
CPU time 2.32 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:10:52 PM PDT 24
Peak memory 196996 kb
Host smart-1a40ba44-7efd-431d-ba6f-8fb12c7f6211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750710948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2750710948
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2287257707
Short name T275
Test name
Test status
Simulation time 162029155 ps
CPU time 0.98 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196040 kb
Host smart-03247220-8fb5-4e54-8005-bb90db75fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287257707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2287257707
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2093755491
Short name T248
Test name
Test status
Simulation time 27137585 ps
CPU time 0.99 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196060 kb
Host smart-932e3cc6-4914-44fb-b155-58645ff2a876
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093755491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2093755491
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1753347141
Short name T209
Test name
Test status
Simulation time 323026062 ps
CPU time 3.99 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 198140 kb
Host smart-c8a0f2e2-1a0d-48f4-a481-2912f86b11a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753347141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1753347141
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2003393817
Short name T96
Test name
Test status
Simulation time 82785004 ps
CPU time 0.83 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196516 kb
Host smart-9650fe90-6895-42f6-bb9f-4ecadab7ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003393817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2003393817
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1909253148
Short name T114
Test name
Test status
Simulation time 51148995 ps
CPU time 0.85 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196568 kb
Host smart-541bca4f-0018-45f3-8437-2388df4486af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909253148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1909253148
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.573079042
Short name T552
Test name
Test status
Simulation time 28112090849 ps
CPU time 187.54 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:13:53 PM PDT 24
Peak memory 198304 kb
Host smart-4ed33e56-7ebb-45d9-9c8a-0e4538faab4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573079042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.573079042
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.4151510186
Short name T27
Test name
Test status
Simulation time 5320289841 ps
CPU time 97.4 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:12:22 PM PDT 24
Peak memory 198512 kb
Host smart-095bcb60-7dba-40d3-b6c0-799989643fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4151510186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.4151510186
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3649952428
Short name T524
Test name
Test status
Simulation time 49713124 ps
CPU time 0.58 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 194968 kb
Host smart-5b4374d3-2f4c-42ea-b50d-deb58f5f152d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649952428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3649952428
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2166448685
Short name T574
Test name
Test status
Simulation time 75458998 ps
CPU time 0.75 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 195300 kb
Host smart-54f78e49-334b-47c1-aee0-72dd821e7979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166448685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2166448685
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3111456260
Short name T227
Test name
Test status
Simulation time 514830583 ps
CPU time 24.73 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 197120 kb
Host smart-14872a5e-be27-42d1-9199-2ecd0d14969f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111456260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3111456260
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2553512228
Short name T380
Test name
Test status
Simulation time 165547478 ps
CPU time 0.85 seconds
Started Aug 16 05:10:57 PM PDT 24
Finished Aug 16 05:10:58 PM PDT 24
Peak memory 197756 kb
Host smart-59013237-4349-40f8-bcc9-3b69ac1d953d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553512228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2553512228
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2410322359
Short name T279
Test name
Test status
Simulation time 313305518 ps
CPU time 0.95 seconds
Started Aug 16 05:10:56 PM PDT 24
Finished Aug 16 05:10:57 PM PDT 24
Peak memory 196160 kb
Host smart-b5ae0872-6a9b-4a8f-8c52-8fb96923a956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410322359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2410322359
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3591306291
Short name T482
Test name
Test status
Simulation time 322565772 ps
CPU time 2.89 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 198080 kb
Host smart-4fc0dfb0-d706-4063-9c83-0ae2975791c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591306291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3591306291
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2028762144
Short name T394
Test name
Test status
Simulation time 100307288 ps
CPU time 2.7 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196036 kb
Host smart-d14d7e2e-93e8-4dba-b2b6-3910da509b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028762144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2028762144
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4293010549
Short name T62
Test name
Test status
Simulation time 47199293 ps
CPU time 1.07 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 195948 kb
Host smart-9ff96b45-3fcd-41f3-9388-c0968e6c9421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293010549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4293010549
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1496741452
Short name T687
Test name
Test status
Simulation time 54101401 ps
CPU time 1.05 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:10:41 PM PDT 24
Peak memory 196064 kb
Host smart-efa85eb2-a954-4215-8d4c-9815c61bdaa1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496741452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1496741452
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3333639648
Short name T486
Test name
Test status
Simulation time 33315821 ps
CPU time 1.43 seconds
Started Aug 16 05:11:02 PM PDT 24
Finished Aug 16 05:11:04 PM PDT 24
Peak memory 198160 kb
Host smart-67068aa3-dcd3-444e-b353-eafc25bffd78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333639648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3333639648
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3900502331
Short name T123
Test name
Test status
Simulation time 221806884 ps
CPU time 0.92 seconds
Started Aug 16 05:10:54 PM PDT 24
Finished Aug 16 05:10:55 PM PDT 24
Peak memory 195832 kb
Host smart-57a1b176-89a7-4300-8b8f-79948805db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900502331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3900502331
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1636361159
Short name T253
Test name
Test status
Simulation time 342830557 ps
CPU time 1.28 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 196548 kb
Host smart-ce260032-bd52-4503-9197-46418cea4874
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636361159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1636361159
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3422578581
Short name T526
Test name
Test status
Simulation time 7781783616 ps
CPU time 117.83 seconds
Started Aug 16 05:10:53 PM PDT 24
Finished Aug 16 05:12:51 PM PDT 24
Peak memory 198536 kb
Host smart-044fd2e7-7263-47d2-98ea-0141e5143288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3422578581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3422578581
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2321099592
Short name T35
Test name
Test status
Simulation time 68016146 ps
CPU time 0.56 seconds
Started Aug 16 05:10:22 PM PDT 24
Finished Aug 16 05:10:23 PM PDT 24
Peak memory 193960 kb
Host smart-9215a185-267d-470f-b1e8-473675a3e077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321099592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2321099592
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.397200299
Short name T460
Test name
Test status
Simulation time 44387677 ps
CPU time 0.82 seconds
Started Aug 16 05:10:23 PM PDT 24
Finished Aug 16 05:10:24 PM PDT 24
Peak memory 195588 kb
Host smart-4c25a751-7bf3-4c3e-b188-f18201f7ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397200299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.397200299
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.541242628
Short name T113
Test name
Test status
Simulation time 2410366805 ps
CPU time 19.57 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 198284 kb
Host smart-9147fb3f-69ee-468f-9e60-f5f657f3d7a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541242628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.541242628
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2414501991
Short name T474
Test name
Test status
Simulation time 23384226 ps
CPU time 0.67 seconds
Started Aug 16 05:10:08 PM PDT 24
Finished Aug 16 05:10:09 PM PDT 24
Peak memory 194568 kb
Host smart-49404277-bebb-463c-baa1-8ed93eefd90c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414501991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2414501991
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.158338724
Short name T52
Test name
Test status
Simulation time 55966595 ps
CPU time 1.02 seconds
Started Aug 16 05:10:14 PM PDT 24
Finished Aug 16 05:10:15 PM PDT 24
Peak memory 196756 kb
Host smart-3d93b08d-2390-4b83-9bdc-1baf0ee1eb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158338724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.158338724
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1903179024
Short name T395
Test name
Test status
Simulation time 82295467 ps
CPU time 3.23 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:30 PM PDT 24
Peak memory 198256 kb
Host smart-dab9436a-dbd5-44ca-a696-f5f125d5ccf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903179024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1903179024
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.148395154
Short name T709
Test name
Test status
Simulation time 155067580 ps
CPU time 2.89 seconds
Started Aug 16 05:10:18 PM PDT 24
Finished Aug 16 05:10:21 PM PDT 24
Peak memory 197148 kb
Host smart-3223b26d-1fba-4637-803d-71f72fdbd6d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148395154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.148395154
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2445175208
Short name T647
Test name
Test status
Simulation time 117121129 ps
CPU time 1.2 seconds
Started Aug 16 05:10:06 PM PDT 24
Finished Aug 16 05:10:07 PM PDT 24
Peak memory 196000 kb
Host smart-7a27338a-34b8-4a62-b8f6-e44015046e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445175208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2445175208
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3092021443
Short name T124
Test name
Test status
Simulation time 112691599 ps
CPU time 0.83 seconds
Started Aug 16 05:10:23 PM PDT 24
Finished Aug 16 05:10:24 PM PDT 24
Peak memory 197220 kb
Host smart-5cc72c07-2628-4eb9-ad56-cf633d9b1d5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092021443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3092021443
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.647980319
Short name T353
Test name
Test status
Simulation time 600313199 ps
CPU time 2.67 seconds
Started Aug 16 05:10:19 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 198100 kb
Host smart-823d7ac7-9f20-4dfb-854d-c0540798dd82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647980319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.647980319
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1286460167
Short name T34
Test name
Test status
Simulation time 58307515 ps
CPU time 0.89 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 214028 kb
Host smart-5c824f55-262d-441b-a78d-c4ede75c0b6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286460167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1286460167
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1727694176
Short name T250
Test name
Test status
Simulation time 785969769 ps
CPU time 1.25 seconds
Started Aug 16 05:10:11 PM PDT 24
Finished Aug 16 05:10:12 PM PDT 24
Peak memory 196972 kb
Host smart-c6e57b94-047e-4659-afb9-b39c5d9d8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727694176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1727694176
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3828286015
Short name T107
Test name
Test status
Simulation time 62585497 ps
CPU time 1.21 seconds
Started Aug 16 05:10:20 PM PDT 24
Finished Aug 16 05:10:21 PM PDT 24
Peak memory 196344 kb
Host smart-8a061795-425f-42b5-a1fb-0b988010c85c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828286015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3828286015
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2949780281
Short name T391
Test name
Test status
Simulation time 18514585921 ps
CPU time 207.12 seconds
Started Aug 16 05:10:17 PM PDT 24
Finished Aug 16 05:13:44 PM PDT 24
Peak memory 198328 kb
Host smart-23d3b623-5924-4132-b9bd-3309d740606f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949780281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2949780281
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3108075065
Short name T352
Test name
Test status
Simulation time 18101260 ps
CPU time 0.59 seconds
Started Aug 16 05:10:42 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 193944 kb
Host smart-e8eae166-92d8-4e39-90f0-2112fcaa7ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108075065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3108075065
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3313762784
Short name T531
Test name
Test status
Simulation time 63938905 ps
CPU time 0.85 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 195596 kb
Host smart-010896fd-822c-41dd-85d7-0873d9dc1997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313762784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3313762784
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2326220818
Short name T300
Test name
Test status
Simulation time 1385586114 ps
CPU time 22.4 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:11:09 PM PDT 24
Peak memory 195656 kb
Host smart-5b7f66a1-19b8-4e3e-9d08-885696607b16
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326220818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2326220818
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1214604311
Short name T565
Test name
Test status
Simulation time 35063865 ps
CPU time 0.73 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 194652 kb
Host smart-8ccf9ecc-28fc-4d5d-a17e-c732451d75f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214604311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1214604311
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2734501576
Short name T189
Test name
Test status
Simulation time 167938995 ps
CPU time 1.32 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 198240 kb
Host smart-3e867db1-4fb3-421d-a255-0fe90904987f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734501576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2734501576
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2629658997
Short name T378
Test name
Test status
Simulation time 32959015 ps
CPU time 1.2 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 197496 kb
Host smart-b68bc9cd-ea8b-475e-ac73-1d7a70818f30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629658997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2629658997
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3131039269
Short name T235
Test name
Test status
Simulation time 244098448 ps
CPU time 3.54 seconds
Started Aug 16 05:10:54 PM PDT 24
Finished Aug 16 05:10:58 PM PDT 24
Peak memory 197156 kb
Host smart-29d15a1e-b83b-4928-9abf-c7596e69dc78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131039269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3131039269
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1354006340
Short name T479
Test name
Test status
Simulation time 20343455 ps
CPU time 0.84 seconds
Started Aug 16 05:10:53 PM PDT 24
Finished Aug 16 05:10:54 PM PDT 24
Peak memory 196504 kb
Host smart-3351f151-9a2c-4338-b72d-8418504b621f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354006340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1354006340
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1373419973
Short name T325
Test name
Test status
Simulation time 84832656 ps
CPU time 1.04 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196824 kb
Host smart-34a3d349-2ecb-4a42-acef-cc6e51dadce3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373419973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1373419973
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1594385806
Short name T102
Test name
Test status
Simulation time 568334513 ps
CPU time 4.7 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:52 PM PDT 24
Peak memory 198132 kb
Host smart-de445006-d403-4344-990b-efcfe901e511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594385806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1594385806
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4079084949
Short name T164
Test name
Test status
Simulation time 44192920 ps
CPU time 0.94 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 195268 kb
Host smart-f2b57ad1-93dd-4692-841e-63519f31f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079084949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4079084949
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2356514617
Short name T466
Test name
Test status
Simulation time 76462513 ps
CPU time 1.23 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 195840 kb
Host smart-b341e83d-8104-4eb9-ae1c-4e32391b33cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356514617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2356514617
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1643681049
Short name T415
Test name
Test status
Simulation time 60762582688 ps
CPU time 157.19 seconds
Started Aug 16 05:10:42 PM PDT 24
Finished Aug 16 05:13:20 PM PDT 24
Peak memory 198188 kb
Host smart-09db244d-d20f-483c-b56c-3acb3becf454
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643681049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1643681049
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2987617277
Short name T635
Test name
Test status
Simulation time 43924823 ps
CPU time 0.57 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:11:00 PM PDT 24
Peak memory 194120 kb
Host smart-583ad320-c34e-43a3-9797-a8021b2d0d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987617277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2987617277
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.382543774
Short name T210
Test name
Test status
Simulation time 87208387 ps
CPU time 0.81 seconds
Started Aug 16 05:10:57 PM PDT 24
Finished Aug 16 05:10:58 PM PDT 24
Peak memory 195600 kb
Host smart-e714c9b7-8551-4573-9dbf-8b65631ecfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382543774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.382543774
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2768074218
Short name T328
Test name
Test status
Simulation time 2729429027 ps
CPU time 18.82 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:11:06 PM PDT 24
Peak memory 197088 kb
Host smart-2e9c4baf-5125-4af0-b9df-4264e2f8aa27
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768074218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2768074218
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.915688408
Short name T345
Test name
Test status
Simulation time 158176479 ps
CPU time 0.72 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:10:56 PM PDT 24
Peak memory 194664 kb
Host smart-d6bfba81-87a9-4294-b657-937ea16ad1fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915688408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.915688408
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1562755270
Short name T558
Test name
Test status
Simulation time 50313590 ps
CPU time 0.65 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:10:56 PM PDT 24
Peak memory 194380 kb
Host smart-3d6fb674-8aaa-4b26-934a-39979fb206d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562755270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1562755270
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.372761664
Short name T341
Test name
Test status
Simulation time 25970987 ps
CPU time 1.1 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 198036 kb
Host smart-e739f749-36ff-4eed-a916-238248471cea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372761664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.372761664
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2409006254
Short name T368
Test name
Test status
Simulation time 103479323 ps
CPU time 1.76 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:17 PM PDT 24
Peak memory 196164 kb
Host smart-379b7482-4511-4101-a2f6-38a7b59ab80a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409006254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2409006254
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2294912306
Short name T335
Test name
Test status
Simulation time 44655696 ps
CPU time 1.07 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 196132 kb
Host smart-33dd9462-4618-4cf0-bc92-15d0fb90d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294912306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2294912306
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1207648585
Short name T651
Test name
Test status
Simulation time 17299194 ps
CPU time 0.64 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:44 PM PDT 24
Peak memory 195064 kb
Host smart-6c45aaa6-1920-4785-adaa-8388890900f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207648585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1207648585
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.197059107
Short name T386
Test name
Test status
Simulation time 2086727340 ps
CPU time 5.8 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:54 PM PDT 24
Peak memory 198008 kb
Host smart-2bc50bd4-1336-4b30-995c-d5d400823321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197059107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.197059107
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4107958348
Short name T226
Test name
Test status
Simulation time 137008535 ps
CPU time 1.38 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196928 kb
Host smart-dd5bfa81-31c5-48cf-9126-d0e37409a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107958348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4107958348
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.385237010
Short name T106
Test name
Test status
Simulation time 268720663 ps
CPU time 0.98 seconds
Started Aug 16 05:11:04 PM PDT 24
Finished Aug 16 05:11:05 PM PDT 24
Peak memory 195824 kb
Host smart-e8434a27-09c7-47bf-b63b-fb7193245cbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385237010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.385237010
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3815914513
Short name T233
Test name
Test status
Simulation time 2884397534 ps
CPU time 43.39 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 198316 kb
Host smart-6945f929-a3df-4ea2-88f8-2b8f8572902b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815914513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3815914513
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2281188605
Short name T569
Test name
Test status
Simulation time 23956926456 ps
CPU time 242.22 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:14:48 PM PDT 24
Peak memory 198516 kb
Host smart-ae6f848c-29bd-4a55-a447-0893ccb9afed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2281188605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2281188605
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2113493946
Short name T554
Test name
Test status
Simulation time 25920382 ps
CPU time 0.55 seconds
Started Aug 16 05:10:53 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 193984 kb
Host smart-5610e526-4e66-4331-bfd9-c300e6ed1c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113493946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2113493946
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.608888722
Short name T402
Test name
Test status
Simulation time 143420570 ps
CPU time 0.83 seconds
Started Aug 16 05:10:46 PM PDT 24
Finished Aug 16 05:10:48 PM PDT 24
Peak memory 196640 kb
Host smart-b0990733-704d-449e-a9ba-58bf29d5d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608888722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.608888722
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2011323723
Short name T459
Test name
Test status
Simulation time 624352424 ps
CPU time 8.45 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 196980 kb
Host smart-043c4f44-a4b5-4eca-a8f0-b63f2b9d8a01
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011323723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2011323723
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1561871646
Short name T93
Test name
Test status
Simulation time 203423733 ps
CPU time 1.14 seconds
Started Aug 16 05:10:43 PM PDT 24
Finished Aug 16 05:10:45 PM PDT 24
Peak memory 196696 kb
Host smart-d4abe343-a394-4e63-b0d0-6ebf6865ac1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561871646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1561871646
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.828037630
Short name T324
Test name
Test status
Simulation time 150152711 ps
CPU time 1.3 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 197556 kb
Host smart-4fdc5905-4951-4318-9e02-6f82ccc739d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828037630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.828037630
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2032202956
Short name T194
Test name
Test status
Simulation time 358124366 ps
CPU time 1.29 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 196744 kb
Host smart-d73ecd0c-9acf-4f41-8f2e-24696ad12d15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032202956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2032202956
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3726463337
Short name T658
Test name
Test status
Simulation time 101286041 ps
CPU time 2.11 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 198200 kb
Host smart-f50cc012-05c1-4563-83ca-806151b8e741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726463337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3726463337
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3463906475
Short name T505
Test name
Test status
Simulation time 67258947 ps
CPU time 1.29 seconds
Started Aug 16 05:10:44 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 197104 kb
Host smart-e520de4e-fe6a-414a-accb-e4df3b92f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463906475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3463906475
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3850653331
Short name T626
Test name
Test status
Simulation time 87457617 ps
CPU time 0.77 seconds
Started Aug 16 05:11:03 PM PDT 24
Finished Aug 16 05:11:04 PM PDT 24
Peak memory 196244 kb
Host smart-78032778-c9af-4768-80e7-51a8d4e4d2aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850653331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3850653331
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3820503582
Short name T480
Test name
Test status
Simulation time 101107602 ps
CPU time 1.74 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 197964 kb
Host smart-9ab9a162-38f8-4345-9364-9bdc80c6e2f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820503582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3820503582
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.169830123
Short name T367
Test name
Test status
Simulation time 102615886 ps
CPU time 0.75 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 195236 kb
Host smart-6d88788e-7ba3-4001-801e-149a81f574f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169830123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.169830123
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3034724013
Short name T523
Test name
Test status
Simulation time 298576975 ps
CPU time 1 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 195832 kb
Host smart-29a29a8d-f6fe-4be0-a085-bfe9050c1252
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034724013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3034724013
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.593288255
Short name T447
Test name
Test status
Simulation time 959046461 ps
CPU time 23.06 seconds
Started Aug 16 05:10:54 PM PDT 24
Finished Aug 16 05:11:18 PM PDT 24
Peak memory 198220 kb
Host smart-e99fc720-3390-482e-aa66-9d4bbdb48115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593288255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.593288255
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3883542049
Short name T55
Test name
Test status
Simulation time 6523378393 ps
CPU time 212.91 seconds
Started Aug 16 05:10:54 PM PDT 24
Finished Aug 16 05:14:27 PM PDT 24
Peak memory 198516 kb
Host smart-9e313d20-f0ed-4a69-a477-9a00d3373856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3883542049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3883542049
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2734953211
Short name T346
Test name
Test status
Simulation time 24452032 ps
CPU time 0.58 seconds
Started Aug 16 05:11:05 PM PDT 24
Finished Aug 16 05:11:05 PM PDT 24
Peak memory 194800 kb
Host smart-8f5d060b-66e6-495d-ada4-8d07d843396c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734953211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2734953211
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.33048592
Short name T122
Test name
Test status
Simulation time 143830635 ps
CPU time 0.77 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:54 PM PDT 24
Peak memory 195340 kb
Host smart-002a67d0-3023-446e-9d2a-ef5043680e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33048592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.33048592
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1072366655
Short name T365
Test name
Test status
Simulation time 2877485055 ps
CPU time 9.97 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:11:00 PM PDT 24
Peak memory 198288 kb
Host smart-8074395e-20ce-484a-9dce-45562a000f8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072366655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1072366655
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1488942382
Short name T450
Test name
Test status
Simulation time 99785804 ps
CPU time 0.67 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 195280 kb
Host smart-0468931f-71bf-4a5f-9e7c-0f8e151328f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488942382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1488942382
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4078863091
Short name T321
Test name
Test status
Simulation time 29050608 ps
CPU time 0.64 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:10:56 PM PDT 24
Peak memory 194368 kb
Host smart-ab259c5c-9f22-4ab1-9b50-484891d706d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078863091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4078863091
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1585961073
Short name T280
Test name
Test status
Simulation time 1107753494 ps
CPU time 2.68 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:10:52 PM PDT 24
Peak memory 198148 kb
Host smart-894865b1-94ed-4968-ba36-5dfd89b603fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585961073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1585961073
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4040105320
Short name T293
Test name
Test status
Simulation time 144766726 ps
CPU time 2.91 seconds
Started Aug 16 05:10:58 PM PDT 24
Finished Aug 16 05:11:01 PM PDT 24
Peak memory 195976 kb
Host smart-f1cae5e4-6d92-4ece-b7c8-508cbe88e126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040105320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4040105320
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.914130055
Short name T396
Test name
Test status
Simulation time 85179456 ps
CPU time 0.93 seconds
Started Aug 16 05:11:02 PM PDT 24
Finished Aug 16 05:11:03 PM PDT 24
Peak memory 196932 kb
Host smart-5bdbadff-019e-4d2f-b81e-c0cc5f843b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914130055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.914130055
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2715298319
Short name T103
Test name
Test status
Simulation time 65744540 ps
CPU time 0.98 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 196248 kb
Host smart-3000a400-3dc9-4283-bb2b-fbd69b134843
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715298319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2715298319
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2594209487
Short name T302
Test name
Test status
Simulation time 130212179 ps
CPU time 2.28 seconds
Started Aug 16 05:11:08 PM PDT 24
Finished Aug 16 05:11:10 PM PDT 24
Peak memory 198060 kb
Host smart-38368d31-f2b0-4aeb-81b7-74a506434cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594209487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2594209487
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3996300739
Short name T334
Test name
Test status
Simulation time 84538836 ps
CPU time 1.19 seconds
Started Aug 16 05:10:45 PM PDT 24
Finished Aug 16 05:10:46 PM PDT 24
Peak memory 195712 kb
Host smart-3c4cfc11-f6d2-4722-b396-a4521642586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996300739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3996300739
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2233847154
Short name T510
Test name
Test status
Simulation time 211134839 ps
CPU time 1.01 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196692 kb
Host smart-33a7c0d3-fa68-415e-aa7d-ef7e42bc3f95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233847154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2233847154
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.765362941
Short name T249
Test name
Test status
Simulation time 5508542635 ps
CPU time 134.38 seconds
Started Aug 16 05:11:04 PM PDT 24
Finished Aug 16 05:13:18 PM PDT 24
Peak memory 198424 kb
Host smart-86a8b76c-e111-4165-851a-a7d30595ec38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765362941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.765362941
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.722901383
Short name T478
Test name
Test status
Simulation time 2171695696 ps
CPU time 78.46 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 197904 kb
Host smart-2940ee62-121b-4d64-a9e9-9417dcefd79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=722901383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.722901383
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4196387333
Short name T487
Test name
Test status
Simulation time 16373328 ps
CPU time 0.57 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 194012 kb
Host smart-1ef4ab56-18c7-4c97-8324-86c193374b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196387333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4196387333
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3491802934
Short name T616
Test name
Test status
Simulation time 206139029 ps
CPU time 0.71 seconds
Started Aug 16 05:10:54 PM PDT 24
Finished Aug 16 05:10:55 PM PDT 24
Peak memory 196084 kb
Host smart-b93829e7-c702-4b1e-ad92-e7f20c540d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491802934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3491802934
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1841367315
Short name T100
Test name
Test status
Simulation time 766848922 ps
CPU time 26.5 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:11:16 PM PDT 24
Peak memory 197140 kb
Host smart-5aebc5bc-dc1c-46c0-9cb2-9a6c9d0f482a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841367315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1841367315
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.277601472
Short name T351
Test name
Test status
Simulation time 85648415 ps
CPU time 0.75 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:10:56 PM PDT 24
Peak memory 196060 kb
Host smart-6494adc9-086b-4942-a8e1-d3dace849d77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277601472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.277601472
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.293064728
Short name T438
Test name
Test status
Simulation time 512201526 ps
CPU time 1.11 seconds
Started Aug 16 05:11:13 PM PDT 24
Finished Aug 16 05:11:14 PM PDT 24
Peak memory 196816 kb
Host smart-b0ce071e-ea66-4bda-971c-53bbdfc35bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293064728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.293064728
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2416628853
Short name T239
Test name
Test status
Simulation time 61524340 ps
CPU time 1.35 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:10:52 PM PDT 24
Peak memory 198196 kb
Host smart-311733b7-8792-4b93-8326-80a40d883ed1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416628853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2416628853
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2614568446
Short name T330
Test name
Test status
Simulation time 589504053 ps
CPU time 3.22 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:52 PM PDT 24
Peak memory 198352 kb
Host smart-5864ca1d-f63d-461d-bd34-700bf4cc581d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614568446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2614568446
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3627611517
Short name T223
Test name
Test status
Simulation time 63046496 ps
CPU time 1.24 seconds
Started Aug 16 05:11:07 PM PDT 24
Finished Aug 16 05:11:08 PM PDT 24
Peak memory 198204 kb
Host smart-e139c396-5c6a-439a-8231-8e676d65f762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627611517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3627611517
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2628119413
Short name T289
Test name
Test status
Simulation time 53798135 ps
CPU time 0.99 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 195960 kb
Host smart-d6dbb220-3335-44f7-aa79-e72b55d9e228
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628119413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2628119413
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1827562962
Short name T183
Test name
Test status
Simulation time 537278762 ps
CPU time 2.43 seconds
Started Aug 16 05:10:47 PM PDT 24
Finished Aug 16 05:10:50 PM PDT 24
Peak memory 198100 kb
Host smart-ac7c95f7-f789-4191-99a9-906f9f7ad258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827562962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1827562962
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.268290055
Short name T236
Test name
Test status
Simulation time 63754520 ps
CPU time 1.28 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196936 kb
Host smart-5ab964f4-d7e5-4e4a-973f-00c088671933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268290055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.268290055
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3741707741
Short name T600
Test name
Test status
Simulation time 160866629 ps
CPU time 1.47 seconds
Started Aug 16 05:11:05 PM PDT 24
Finished Aug 16 05:11:07 PM PDT 24
Peak memory 196960 kb
Host smart-b1c89fef-e672-4953-967d-780c325d5826
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741707741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3741707741
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.585361604
Short name T639
Test name
Test status
Simulation time 6291943704 ps
CPU time 65.34 seconds
Started Aug 16 05:11:08 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 198324 kb
Host smart-278da169-0d63-418f-a801-9bc62ace54c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585361604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.585361604
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3646497654
Short name T497
Test name
Test status
Simulation time 53656952 ps
CPU time 0.57 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:10:55 PM PDT 24
Peak memory 194236 kb
Host smart-43d4e513-61b9-491b-98de-c37a0154d9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646497654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3646497654
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3162281402
Short name T680
Test name
Test status
Simulation time 149073215 ps
CPU time 0.81 seconds
Started Aug 16 05:11:01 PM PDT 24
Finished Aug 16 05:11:02 PM PDT 24
Peak memory 195500 kb
Host smart-3ed10fb4-44fe-4646-add3-a067a3710fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162281402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3162281402
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1653947364
Short name T119
Test name
Test status
Simulation time 1046551721 ps
CPU time 19.72 seconds
Started Aug 16 05:10:57 PM PDT 24
Finished Aug 16 05:11:17 PM PDT 24
Peak memory 197076 kb
Host smart-e6cbca85-1fbf-46be-876d-270043367b4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653947364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1653947364
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4095312505
Short name T23
Test name
Test status
Simulation time 41049737 ps
CPU time 0.63 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 195228 kb
Host smart-2ad35399-62c4-4980-8c6b-c545b1540e9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095312505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4095312505
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.351012948
Short name T376
Test name
Test status
Simulation time 175328110 ps
CPU time 1.3 seconds
Started Aug 16 05:11:01 PM PDT 24
Finished Aug 16 05:11:02 PM PDT 24
Peak memory 197392 kb
Host smart-3b9c802f-e717-4bc9-b0ae-86ffc8c52b00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351012948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.351012948
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.719790506
Short name T295
Test name
Test status
Simulation time 227577030 ps
CPU time 2.28 seconds
Started Aug 16 05:10:52 PM PDT 24
Finished Aug 16 05:11:00 PM PDT 24
Peak memory 198184 kb
Host smart-ba6a6e30-aa1b-4677-a406-ad4d9211fd54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719790506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.719790506
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4021135711
Short name T117
Test name
Test status
Simulation time 510747473 ps
CPU time 1.37 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196692 kb
Host smart-11ce37bb-8c87-48a5-a944-09f942a96e24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021135711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4021135711
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1206166322
Short name T545
Test name
Test status
Simulation time 150417493 ps
CPU time 0.93 seconds
Started Aug 16 05:11:07 PM PDT 24
Finished Aug 16 05:11:08 PM PDT 24
Peak memory 196836 kb
Host smart-6df23933-8695-4fa7-bea1-383b3424f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206166322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1206166322
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2660582193
Short name T307
Test name
Test status
Simulation time 66577472 ps
CPU time 1.33 seconds
Started Aug 16 05:10:55 PM PDT 24
Finished Aug 16 05:10:57 PM PDT 24
Peak memory 197076 kb
Host smart-1b247b7c-c1b5-4a9a-96f5-66d61f6ea1df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660582193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2660582193
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4006793629
Short name T306
Test name
Test status
Simulation time 450229361 ps
CPU time 3.13 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 198132 kb
Host smart-01273d0a-c5e2-41dc-ad62-870cf25cf568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006793629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4006793629
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2942521383
Short name T254
Test name
Test status
Simulation time 91167468 ps
CPU time 1.32 seconds
Started Aug 16 05:10:49 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 198176 kb
Host smart-8be1b7f5-8f1a-482f-898b-4efd9f830748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942521383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2942521383
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3932543917
Short name T288
Test name
Test status
Simulation time 47581355 ps
CPU time 1.03 seconds
Started Aug 16 05:11:05 PM PDT 24
Finished Aug 16 05:11:06 PM PDT 24
Peak memory 196404 kb
Host smart-2b0d2343-86ac-40c7-8d0b-b2c5102a667c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932543917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3932543917
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.862816553
Short name T286
Test name
Test status
Simulation time 20533096398 ps
CPU time 125.73 seconds
Started Aug 16 05:11:00 PM PDT 24
Finished Aug 16 05:13:06 PM PDT 24
Peak memory 198344 kb
Host smart-2a36efd1-a621-4ab6-a449-c677610433a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862816553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.862816553
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2131010625
Short name T690
Test name
Test status
Simulation time 23227356 ps
CPU time 0.57 seconds
Started Aug 16 05:11:12 PM PDT 24
Finished Aug 16 05:11:13 PM PDT 24
Peak memory 193988 kb
Host smart-8486bb2a-7706-4694-89de-3855bef74d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131010625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2131010625
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2314397265
Short name T26
Test name
Test status
Simulation time 347995890 ps
CPU time 0.95 seconds
Started Aug 16 05:11:00 PM PDT 24
Finished Aug 16 05:11:01 PM PDT 24
Peak memory 196020 kb
Host smart-b4f5da1c-43d4-4df6-97fc-015971b057e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314397265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2314397265
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.560612687
Short name T238
Test name
Test status
Simulation time 1010577627 ps
CPU time 23.37 seconds
Started Aug 16 05:11:03 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 196924 kb
Host smart-bf97bef6-d575-4eca-bed3-40a51ec2cf45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560612687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.560612687
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2031442655
Short name T297
Test name
Test status
Simulation time 384457469 ps
CPU time 0.74 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:17 PM PDT 24
Peak memory 194784 kb
Host smart-15f88aed-d252-4cfc-8030-b64390324bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031442655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2031442655
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.460943344
Short name T101
Test name
Test status
Simulation time 61261895 ps
CPU time 0.89 seconds
Started Aug 16 05:11:14 PM PDT 24
Finished Aug 16 05:11:15 PM PDT 24
Peak memory 195508 kb
Host smart-4f21ddad-b76d-4f72-a16b-ed61f97fb3f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460943344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.460943344
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1176468500
Short name T549
Test name
Test status
Simulation time 54570939 ps
CPU time 1.71 seconds
Started Aug 16 05:10:52 PM PDT 24
Finished Aug 16 05:10:54 PM PDT 24
Peak memory 197360 kb
Host smart-306b6754-e0f9-4cd0-b7e5-7407804647ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176468500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1176468500
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2161694439
Short name T301
Test name
Test status
Simulation time 371828179 ps
CPU time 1.87 seconds
Started Aug 16 05:11:06 PM PDT 24
Finished Aug 16 05:11:08 PM PDT 24
Peak memory 197100 kb
Host smart-2e8357e5-7ae0-4ef7-b860-c275e2ccc7fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161694439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2161694439
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2708720180
Short name T143
Test name
Test status
Simulation time 146127614 ps
CPU time 0.8 seconds
Started Aug 16 05:10:52 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 196276 kb
Host smart-1d4df14f-fcd3-4923-ab22-e4f3eefdec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708720180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2708720180
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4247183201
Short name T54
Test name
Test status
Simulation time 26844661 ps
CPU time 0.8 seconds
Started Aug 16 05:10:48 PM PDT 24
Finished Aug 16 05:10:49 PM PDT 24
Peak memory 196328 kb
Host smart-3545f6d7-1031-49d3-8181-92079477acbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247183201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4247183201
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3565552049
Short name T530
Test name
Test status
Simulation time 466944644 ps
CPU time 4.49 seconds
Started Aug 16 05:11:04 PM PDT 24
Finished Aug 16 05:11:08 PM PDT 24
Peak memory 197908 kb
Host smart-2e4fd36a-f298-4c3c-a5f8-af452292ef96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565552049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3565552049
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2240227621
Short name T343
Test name
Test status
Simulation time 38773101 ps
CPU time 1.09 seconds
Started Aug 16 05:10:50 PM PDT 24
Finished Aug 16 05:10:51 PM PDT 24
Peak memory 195904 kb
Host smart-8aa16eee-b6f4-4572-902b-d7eed92e34a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240227621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2240227621
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1068284862
Short name T48
Test name
Test status
Simulation time 83096944 ps
CPU time 1.33 seconds
Started Aug 16 05:10:56 PM PDT 24
Finished Aug 16 05:10:58 PM PDT 24
Peak memory 198116 kb
Host smart-a6f23d5a-df45-4bc4-8cd3-d1d4e7e19b3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068284862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1068284862
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2973873367
Short name T551
Test name
Test status
Simulation time 21024174291 ps
CPU time 68.32 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:12:19 PM PDT 24
Peak memory 198344 kb
Host smart-9fc8e909-a57f-442f-ac04-3e65ea3b57ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973873367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2973873367
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3705675067
Short name T311
Test name
Test status
Simulation time 24010775 ps
CPU time 0.56 seconds
Started Aug 16 05:11:09 PM PDT 24
Finished Aug 16 05:11:09 PM PDT 24
Peak memory 194220 kb
Host smart-3f6a1663-a982-457b-b67c-aa9376869b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705675067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3705675067
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3082615750
Short name T588
Test name
Test status
Simulation time 163429577 ps
CPU time 0.93 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 195876 kb
Host smart-78740b52-2d36-45d1-b0e7-e5fd576e57ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082615750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3082615750
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1698509462
Short name T105
Test name
Test status
Simulation time 971620635 ps
CPU time 5.2 seconds
Started Aug 16 05:11:19 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 196776 kb
Host smart-dd2e02e7-ef33-45ec-bca6-d23a42b3996b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698509462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1698509462
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.849235331
Short name T205
Test name
Test status
Simulation time 55995114 ps
CPU time 0.89 seconds
Started Aug 16 05:11:09 PM PDT 24
Finished Aug 16 05:11:10 PM PDT 24
Peak memory 196980 kb
Host smart-4355a28d-ad1b-418e-a65c-6c1b010cd728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849235331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.849235331
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3735969125
Short name T667
Test name
Test status
Simulation time 246128029 ps
CPU time 0.8 seconds
Started Aug 16 05:11:08 PM PDT 24
Finished Aug 16 05:11:09 PM PDT 24
Peak memory 195632 kb
Host smart-16bc4b83-bd87-465a-a905-902e45bb4c0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735969125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3735969125
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3266733942
Short name T465
Test name
Test status
Simulation time 31823266 ps
CPU time 1.06 seconds
Started Aug 16 05:11:14 PM PDT 24
Finished Aug 16 05:11:15 PM PDT 24
Peak memory 196972 kb
Host smart-ae2516d7-7b89-4d8e-8f31-6ada669e42d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266733942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3266733942
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1487441567
Short name T404
Test name
Test status
Simulation time 676133425 ps
CPU time 3.16 seconds
Started Aug 16 05:11:14 PM PDT 24
Finished Aug 16 05:11:17 PM PDT 24
Peak memory 195948 kb
Host smart-18407848-cff8-41d8-acb6-e922a02e67c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487441567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1487441567
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2114018592
Short name T242
Test name
Test status
Simulation time 23396278 ps
CPU time 0.75 seconds
Started Aug 16 05:11:10 PM PDT 24
Finished Aug 16 05:11:11 PM PDT 24
Peak memory 195380 kb
Host smart-328c2dd5-5597-4fbe-b831-60b8a5389df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114018592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2114018592
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1452101867
Short name T628
Test name
Test status
Simulation time 26023508 ps
CPU time 0.73 seconds
Started Aug 16 05:11:13 PM PDT 24
Finished Aug 16 05:11:14 PM PDT 24
Peak memory 196224 kb
Host smart-049b5954-196e-46b8-b47a-763eb128c4ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452101867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1452101867
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2785999846
Short name T695
Test name
Test status
Simulation time 142718673 ps
CPU time 2.57 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:19 PM PDT 24
Peak memory 198172 kb
Host smart-91fb5b0b-078f-443f-b1b4-93c556777759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785999846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2785999846
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3415027559
Short name T332
Test name
Test status
Simulation time 115646639 ps
CPU time 1.21 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 195948 kb
Host smart-35eb872f-acb6-4add-b852-5adf5465fe1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415027559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3415027559
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2185330664
Short name T650
Test name
Test status
Simulation time 209875615 ps
CPU time 1.47 seconds
Started Aug 16 05:11:08 PM PDT 24
Finished Aug 16 05:11:10 PM PDT 24
Peak memory 198180 kb
Host smart-742a5e2b-04af-4466-9f73-093b44515df5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185330664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2185330664
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2637324264
Short name T381
Test name
Test status
Simulation time 2907407663 ps
CPU time 73.05 seconds
Started Aug 16 05:11:07 PM PDT 24
Finished Aug 16 05:12:20 PM PDT 24
Peak memory 198332 kb
Host smart-34951889-8056-419a-91e4-edc364ec6603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637324264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2637324264
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.4139135447
Short name T264
Test name
Test status
Simulation time 53245721 ps
CPU time 0.57 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 194752 kb
Host smart-86968e2d-29f8-4b0f-9e5b-b0af469deb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139135447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4139135447
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1395256699
Short name T137
Test name
Test status
Simulation time 30255919 ps
CPU time 0.72 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:11:11 PM PDT 24
Peak memory 194168 kb
Host smart-76d42b33-1374-4ed6-9229-77dab6651233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395256699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1395256699
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3720342415
Short name T98
Test name
Test status
Simulation time 883624393 ps
CPU time 27.22 seconds
Started Aug 16 05:11:08 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 198188 kb
Host smart-b21070f7-d8a6-437a-a2d1-fbbf8c11c700
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720342415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3720342415
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3499260678
Short name T99
Test name
Test status
Simulation time 90595602 ps
CPU time 0.92 seconds
Started Aug 16 05:11:04 PM PDT 24
Finished Aug 16 05:11:05 PM PDT 24
Peak memory 197312 kb
Host smart-1987aa36-eb87-4fcb-b6cb-543cf99f6271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499260678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3499260678
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2898089345
Short name T198
Test name
Test status
Simulation time 23714175 ps
CPU time 0.65 seconds
Started Aug 16 05:11:04 PM PDT 24
Finished Aug 16 05:11:05 PM PDT 24
Peak memory 194424 kb
Host smart-4a9bcacc-002d-496d-810d-d87fc416e5ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898089345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2898089345
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3167969471
Short name T409
Test name
Test status
Simulation time 259995284 ps
CPU time 1.7 seconds
Started Aug 16 05:11:19 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 196372 kb
Host smart-3124bafc-0bc0-4916-a4b7-fa122824fb36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167969471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3167969471
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3770920771
Short name T615
Test name
Test status
Simulation time 170106596 ps
CPU time 2.5 seconds
Started Aug 16 05:11:10 PM PDT 24
Finished Aug 16 05:11:13 PM PDT 24
Peak memory 195964 kb
Host smart-158253b0-e127-4da7-b23a-91ae9524e0eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770920771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3770920771
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.22561290
Short name T560
Test name
Test status
Simulation time 69753194 ps
CPU time 0.79 seconds
Started Aug 16 05:11:19 PM PDT 24
Finished Aug 16 05:11:20 PM PDT 24
Peak memory 196664 kb
Host smart-ea49d429-1daa-4e46-bb11-4fdc1f707f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22561290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.22561290
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1866366173
Short name T426
Test name
Test status
Simulation time 84670722 ps
CPU time 0.85 seconds
Started Aug 16 05:11:18 PM PDT 24
Finished Aug 16 05:11:19 PM PDT 24
Peak memory 195956 kb
Host smart-d6013b04-17fc-477d-af72-65e83f35b8f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866366173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1866366173
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3242363234
Short name T327
Test name
Test status
Simulation time 1431533884 ps
CPU time 4.16 seconds
Started Aug 16 05:11:13 PM PDT 24
Finished Aug 16 05:11:17 PM PDT 24
Peak memory 198128 kb
Host smart-aed46a3e-75ad-4043-a30f-76f43bf5f77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242363234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3242363234
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3569647257
Short name T166
Test name
Test status
Simulation time 88759465 ps
CPU time 1.29 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 197084 kb
Host smart-f2172ad5-baea-43a6-b1fb-6f9b5cbc974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569647257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3569647257
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2820164778
Short name T276
Test name
Test status
Simulation time 47213088 ps
CPU time 1.28 seconds
Started Aug 16 05:10:58 PM PDT 24
Finished Aug 16 05:10:59 PM PDT 24
Peak memory 196992 kb
Host smart-ce0b0de5-2482-4298-bd7b-d1334093f533
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820164778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2820164778
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.95421024
Short name T375
Test name
Test status
Simulation time 7764295129 ps
CPU time 105.37 seconds
Started Aug 16 05:11:09 PM PDT 24
Finished Aug 16 05:12:54 PM PDT 24
Peak memory 198356 kb
Host smart-edce941f-b347-49dd-8561-9482ff93b024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95421024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gp
io_stress_all.95421024
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1846359546
Short name T333
Test name
Test status
Simulation time 26806869 ps
CPU time 0.58 seconds
Started Aug 16 05:11:18 PM PDT 24
Finished Aug 16 05:11:19 PM PDT 24
Peak memory 194212 kb
Host smart-abace198-b740-4420-ab8e-ad453c005c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846359546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1846359546
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2240897640
Short name T424
Test name
Test status
Simulation time 173665238 ps
CPU time 0.86 seconds
Started Aug 16 05:11:14 PM PDT 24
Finished Aug 16 05:11:15 PM PDT 24
Peak memory 196528 kb
Host smart-a26a9a48-2f79-445d-a724-5ce6c87c4954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240897640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2240897640
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1939981152
Short name T19
Test name
Test status
Simulation time 459526258 ps
CPU time 7.22 seconds
Started Aug 16 05:11:22 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 195600 kb
Host smart-960e23db-be02-4caf-87a8-02fe0eb32021
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939981152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1939981152
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1769104731
Short name T489
Test name
Test status
Simulation time 140708663 ps
CPU time 1.08 seconds
Started Aug 16 05:11:17 PM PDT 24
Finished Aug 16 05:11:18 PM PDT 24
Peak memory 197192 kb
Host smart-02ebf273-b741-4071-8ba2-a58491ca0ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769104731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1769104731
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1536924187
Short name T666
Test name
Test status
Simulation time 1363022576 ps
CPU time 1.41 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:18 PM PDT 24
Peak memory 198232 kb
Host smart-5555c41a-9e82-42c8-b4eb-376d0502d743
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536924187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1536924187
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3241746189
Short name T53
Test name
Test status
Simulation time 892148636 ps
CPU time 2.3 seconds
Started Aug 16 05:11:12 PM PDT 24
Finished Aug 16 05:11:15 PM PDT 24
Peak memory 198148 kb
Host smart-bbb1f6df-ba2b-45f6-9fac-b4d74d86755b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241746189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3241746189
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.5917745
Short name T287
Test name
Test status
Simulation time 1576827586 ps
CPU time 1.77 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 196092 kb
Host smart-9fa5e590-1638-4cb0-b787-b75b99db2bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5917745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.5917745
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4173101270
Short name T195
Test name
Test status
Simulation time 86532816 ps
CPU time 0.98 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 195924 kb
Host smart-1530ede0-736f-4fb9-815d-4a18b8c61665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173101270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4173101270
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1762915396
Short name T234
Test name
Test status
Simulation time 35844454 ps
CPU time 1.34 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:23 PM PDT 24
Peak memory 197116 kb
Host smart-fe875b2e-c081-4263-9712-0dfe925ec08a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762915396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1762915396
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.995213985
Short name T259
Test name
Test status
Simulation time 395868683 ps
CPU time 3.59 seconds
Started Aug 16 05:11:12 PM PDT 24
Finished Aug 16 05:11:16 PM PDT 24
Peak memory 198132 kb
Host smart-eb998285-6610-447e-b2a3-085d771d756a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995213985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.995213985
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3463825359
Short name T213
Test name
Test status
Simulation time 106633184 ps
CPU time 1.17 seconds
Started Aug 16 05:11:12 PM PDT 24
Finished Aug 16 05:11:13 PM PDT 24
Peak memory 196624 kb
Host smart-9809e3a9-8a6a-4982-83a3-e5890c06fb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463825359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3463825359
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1034984631
Short name T172
Test name
Test status
Simulation time 34679395 ps
CPU time 1 seconds
Started Aug 16 05:11:10 PM PDT 24
Finished Aug 16 05:11:11 PM PDT 24
Peak memory 195964 kb
Host smart-0fc1c4c4-e534-4b5c-885b-198c5b20b0b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034984631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1034984631
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2172223170
Short name T496
Test name
Test status
Simulation time 51732260821 ps
CPU time 177.41 seconds
Started Aug 16 05:11:19 PM PDT 24
Finished Aug 16 05:14:17 PM PDT 24
Peak memory 198260 kb
Host smart-748c71b7-9cf6-4525-b824-a2e2ea0f35c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172223170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2172223170
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.981953616
Short name T646
Test name
Test status
Simulation time 20954384 ps
CPU time 0.58 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:14 PM PDT 24
Peak memory 194048 kb
Host smart-7300ce38-ac1f-4f57-9476-9b6b7425ee29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981953616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.981953616
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2555173477
Short name T65
Test name
Test status
Simulation time 25596692 ps
CPU time 0.67 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:14 PM PDT 24
Peak memory 194940 kb
Host smart-839be905-8622-48d4-ab43-c1925033d5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555173477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2555173477
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1030802224
Short name T630
Test name
Test status
Simulation time 624305147 ps
CPU time 17.28 seconds
Started Aug 16 05:10:18 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 197084 kb
Host smart-0c34f523-1c40-4fcb-9b45-2a88c46349ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030802224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1030802224
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.822879983
Short name T371
Test name
Test status
Simulation time 207365642 ps
CPU time 0.87 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:27 PM PDT 24
Peak memory 197128 kb
Host smart-54f17b91-0c41-46c7-a1a9-126f930213b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822879983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.822879983
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1922456713
Short name T661
Test name
Test status
Simulation time 133867415 ps
CPU time 1.18 seconds
Started Aug 16 05:10:22 PM PDT 24
Finished Aug 16 05:10:23 PM PDT 24
Peak memory 196952 kb
Host smart-cf23866b-12ab-4ae9-b5e5-a291c10c85e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922456713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1922456713
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3031606715
Short name T277
Test name
Test status
Simulation time 270574447 ps
CPU time 2.82 seconds
Started Aug 16 05:10:19 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 198292 kb
Host smart-97afb0f4-8f37-4914-b033-dfa5582c322f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031606715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3031606715
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1047980852
Short name T206
Test name
Test status
Simulation time 338075429 ps
CPU time 2.56 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:27 PM PDT 24
Peak memory 196988 kb
Host smart-c218b7c5-2478-4e28-88a8-bda8569a377a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047980852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1047980852
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1227711903
Short name T590
Test name
Test status
Simulation time 58321367 ps
CPU time 0.64 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 194412 kb
Host smart-28c7aa75-0850-4726-baec-9c484e57595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227711903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1227711903
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2354324486
Short name T504
Test name
Test status
Simulation time 47343868 ps
CPU time 0.99 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 196056 kb
Host smart-1a7740c9-4ec6-452a-aee3-19300c467cf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354324486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2354324486
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3753172651
Short name T140
Test name
Test status
Simulation time 218945540 ps
CPU time 4.69 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 198168 kb
Host smart-1ef1e6eb-09f0-491c-bf22-2872270c4934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753172651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3753172651
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2100258223
Short name T33
Test name
Test status
Simulation time 98690874 ps
CPU time 0.93 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:14 PM PDT 24
Peak memory 215084 kb
Host smart-32d131e8-5df0-4e37-87fd-801b2adb43c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100258223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2100258223
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2348293750
Short name T543
Test name
Test status
Simulation time 143979984 ps
CPU time 1.23 seconds
Started Aug 16 05:10:18 PM PDT 24
Finished Aug 16 05:10:19 PM PDT 24
Peak memory 197288 kb
Host smart-62f5dba1-ad61-4de2-bc15-24a2461381b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348293750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2348293750
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2159173031
Short name T161
Test name
Test status
Simulation time 67449358 ps
CPU time 1.31 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 196764 kb
Host smart-62b4af4f-8601-4623-8969-2a363bed4cab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159173031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2159173031
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1950121805
Short name T338
Test name
Test status
Simulation time 10068455404 ps
CPU time 31.7 seconds
Started Aug 16 05:10:15 PM PDT 24
Finished Aug 16 05:10:47 PM PDT 24
Peak memory 198332 kb
Host smart-b8aa45ff-dd4c-4f5b-b52b-a10e47a866ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950121805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1950121805
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.464762533
Short name T145
Test name
Test status
Simulation time 52832227 ps
CPU time 0.6 seconds
Started Aug 16 05:11:15 PM PDT 24
Finished Aug 16 05:11:16 PM PDT 24
Peak memory 194068 kb
Host smart-bcdc4dfa-9cd4-40a4-8425-a191d3dd0185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464762533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.464762533
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.345358384
Short name T231
Test name
Test status
Simulation time 22915667 ps
CPU time 0.69 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 194240 kb
Host smart-a779f4a0-1b97-4825-9686-058e0d3d4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345358384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.345358384
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2755059379
Short name T689
Test name
Test status
Simulation time 750850699 ps
CPU time 18.36 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 196432 kb
Host smart-7617fece-00ef-4156-bbc1-5fa3298524ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755059379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2755059379
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2556730233
Short name T556
Test name
Test status
Simulation time 39677670 ps
CPU time 0.62 seconds
Started Aug 16 05:11:07 PM PDT 24
Finished Aug 16 05:11:07 PM PDT 24
Peak memory 194484 kb
Host smart-7c37879a-c767-459a-b96e-4e015f7e04a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556730233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2556730233
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3071872898
Short name T602
Test name
Test status
Simulation time 155999618 ps
CPU time 1.06 seconds
Started Aug 16 05:11:15 PM PDT 24
Finished Aug 16 05:11:16 PM PDT 24
Peak memory 196132 kb
Host smart-9a7d72b7-ce22-4111-b5e2-ff6dfe6c3d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071872898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3071872898
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.981841003
Short name T469
Test name
Test status
Simulation time 129854317 ps
CPU time 1.42 seconds
Started Aug 16 05:11:22 PM PDT 24
Finished Aug 16 05:11:23 PM PDT 24
Peak memory 198216 kb
Host smart-0c1d92d3-af53-40eb-90e2-6d20478ec4e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981841003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.981841003
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1573842230
Short name T490
Test name
Test status
Simulation time 107864213 ps
CPU time 0.84 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 194472 kb
Host smart-39bffa96-d746-4953-a223-75d56dd1d639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573842230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1573842230
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.399989038
Short name T176
Test name
Test status
Simulation time 62943952 ps
CPU time 1.12 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 195952 kb
Host smart-46fd6e80-fc3f-4d42-9413-91883e832db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399989038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.399989038
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.738584834
Short name T664
Test name
Test status
Simulation time 34841610 ps
CPU time 1.15 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 196240 kb
Host smart-7ae76910-f116-4c3e-9f8a-a012cd656d49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738584834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.738584834
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4100012874
Short name T685
Test name
Test status
Simulation time 244582559 ps
CPU time 3.35 seconds
Started Aug 16 05:11:08 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 197768 kb
Host smart-8875b323-5ea9-4648-8956-7e266191a13e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100012874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4100012874
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.413085871
Short name T596
Test name
Test status
Simulation time 116344988 ps
CPU time 1.04 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 195768 kb
Host smart-0f71d003-6f9b-4ccf-9403-0000f9726fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413085871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.413085871
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4088709511
Short name T149
Test name
Test status
Simulation time 50131040 ps
CPU time 1.31 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 196696 kb
Host smart-654c12db-3d12-4ddd-9d8e-3d7b650f1759
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088709511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4088709511
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1598798296
Short name T292
Test name
Test status
Simulation time 23707501357 ps
CPU time 114.72 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:13:18 PM PDT 24
Peak memory 198364 kb
Host smart-ab82ca4b-cf98-4c0c-bfd1-b585c92c192f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598798296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1598798296
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.403523058
Short name T400
Test name
Test status
Simulation time 12794059 ps
CPU time 0.59 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 194744 kb
Host smart-0670909d-23b8-4da9-923e-8f5e4ac3eaf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403523058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.403523058
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1897641839
Short name T561
Test name
Test status
Simulation time 112931560 ps
CPU time 0.76 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 195464 kb
Host smart-7638c7d6-ab43-4104-935d-8b1c4222e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897641839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1897641839
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.737717373
Short name T337
Test name
Test status
Simulation time 719514266 ps
CPU time 6.9 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:23 PM PDT 24
Peak memory 197120 kb
Host smart-db942fe7-eacc-49bb-ad5f-6e2f9d07ff37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737717373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.737717373
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2923746600
Short name T451
Test name
Test status
Simulation time 209760832 ps
CPU time 0.75 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 194868 kb
Host smart-5585ee7d-d8c8-41d4-9e19-0df14554def5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923746600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2923746600
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3639266762
Short name T258
Test name
Test status
Simulation time 170736309 ps
CPU time 1.25 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 195968 kb
Host smart-aec0c64c-20b9-4b7a-bb3e-bf2193b27eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639266762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3639266762
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.4036678125
Short name T215
Test name
Test status
Simulation time 1119197448 ps
CPU time 3.13 seconds
Started Aug 16 05:11:24 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 198164 kb
Host smart-ed69eede-9975-4bf9-a943-b83bf2f15426
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036678125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.4036678125
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2415020234
Short name T403
Test name
Test status
Simulation time 516213973 ps
CPU time 2.49 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 196944 kb
Host smart-e1ad786a-1cbe-45f6-a068-7ee25f3cc092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415020234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2415020234
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.945815489
Short name T475
Test name
Test status
Simulation time 28713903 ps
CPU time 0.74 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 195600 kb
Host smart-bf59260f-5b97-43d5-80b7-6fb6d1a44f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945815489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.945815489
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4240747079
Short name T601
Test name
Test status
Simulation time 155262488 ps
CPU time 1.01 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:22 PM PDT 24
Peak memory 196144 kb
Host smart-d214409f-6aad-49a3-a3da-613efb6d5fd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240747079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4240747079
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3542711555
Short name T224
Test name
Test status
Simulation time 142234828 ps
CPU time 1.57 seconds
Started Aug 16 05:11:10 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 196488 kb
Host smart-b02592ca-ce9a-4611-9af9-3abfeb0d62ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542711555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3542711555
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1211747087
Short name T618
Test name
Test status
Simulation time 107603210 ps
CPU time 0.82 seconds
Started Aug 16 05:11:13 PM PDT 24
Finished Aug 16 05:11:14 PM PDT 24
Peak memory 195512 kb
Host smart-1a8f61b6-95c8-4ef6-afa6-45faf4512809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211747087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1211747087
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4280942913
Short name T455
Test name
Test status
Simulation time 50309006 ps
CPU time 1.06 seconds
Started Aug 16 05:11:11 PM PDT 24
Finished Aug 16 05:11:12 PM PDT 24
Peak memory 195888 kb
Host smart-101dcf70-3105-4c16-a301-b633b95694fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280942913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4280942913
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.884761475
Short name T318
Test name
Test status
Simulation time 27346863415 ps
CPU time 95.55 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:12:58 PM PDT 24
Peak memory 198376 kb
Host smart-711f9a54-0a99-4dd5-b758-ec748fde10d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884761475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.884761475
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2457071693
Short name T61
Test name
Test status
Simulation time 26604875183 ps
CPU time 218.53 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:15:02 PM PDT 24
Peak memory 198428 kb
Host smart-ac283fed-ca6c-4e3e-978c-e1692570af83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2457071693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2457071693
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1162471431
Short name T538
Test name
Test status
Simulation time 113097237 ps
CPU time 0.61 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 194276 kb
Host smart-25dfc328-8423-4397-b883-0a9138e1783d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162471431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1162471431
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1982970387
Short name T434
Test name
Test status
Simulation time 16925307 ps
CPU time 0.66 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 194216 kb
Host smart-990a6c2e-b62d-4019-be96-c6b29c7d6f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982970387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1982970387
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2581486183
Short name T541
Test name
Test status
Simulation time 1422968344 ps
CPU time 5.47 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 195696 kb
Host smart-dc561cd3-6f7d-49eb-9801-9694bf77fcdd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581486183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2581486183
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.410852931
Short name T419
Test name
Test status
Simulation time 62470277 ps
CPU time 0.74 seconds
Started Aug 16 05:11:18 PM PDT 24
Finished Aug 16 05:11:19 PM PDT 24
Peak memory 195620 kb
Host smart-23f0ab7a-de06-4e89-9831-338ea5c27f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410852931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.410852931
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4216359905
Short name T659
Test name
Test status
Simulation time 152376172 ps
CPU time 1.23 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:18 PM PDT 24
Peak memory 195936 kb
Host smart-06e6841d-643a-4d80-b19e-34cdd8b5a458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216359905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4216359905
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1111483285
Short name T133
Test name
Test status
Simulation time 131908332 ps
CPU time 2.77 seconds
Started Aug 16 05:11:22 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 196552 kb
Host smart-94da22f0-ca30-42c7-9a0e-ff0345693d39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111483285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1111483285
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2111775992
Short name T241
Test name
Test status
Simulation time 921632674 ps
CPU time 3.75 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 197392 kb
Host smart-a4ed6714-b0ab-41b0-b59e-89c0b20d914a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111775992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2111775992
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.565860378
Short name T449
Test name
Test status
Simulation time 452508041 ps
CPU time 0.85 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 196888 kb
Host smart-c9a323f5-6846-4cce-81d0-ca04899679f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565860378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.565860378
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.617245539
Short name T348
Test name
Test status
Simulation time 230378557 ps
CPU time 0.97 seconds
Started Aug 16 05:11:13 PM PDT 24
Finished Aug 16 05:11:14 PM PDT 24
Peak memory 196144 kb
Host smart-e5259c4f-9a9e-4c6a-b008-ced9e60442f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617245539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.617245539
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2491647015
Short name T315
Test name
Test status
Simulation time 733833991 ps
CPU time 4.9 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 198144 kb
Host smart-578bce51-50f3-4752-b0d6-769188903a1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491647015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2491647015
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.911324562
Short name T372
Test name
Test status
Simulation time 33144738 ps
CPU time 0.96 seconds
Started Aug 16 05:11:24 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 196480 kb
Host smart-36bfb30d-287c-4c08-9859-f040e9e065ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911324562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.911324562
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.25578883
Short name T284
Test name
Test status
Simulation time 24167300 ps
CPU time 0.81 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 195480 kb
Host smart-2c8800f7-9ee5-4446-aed9-ac1814b36e8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25578883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.25578883
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2742111798
Short name T614
Test name
Test status
Simulation time 17970789376 ps
CPU time 203.93 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:14:40 PM PDT 24
Peak memory 198336 kb
Host smart-a6073b4e-f96d-4c69-bc55-6a55b01632fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742111798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2742111798
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1800087029
Short name T384
Test name
Test status
Simulation time 5151947117 ps
CPU time 46.16 seconds
Started Aug 16 05:11:22 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 198512 kb
Host smart-702113e2-c688-4fb2-908a-74e4224c20f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1800087029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1800087029
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1511696420
Short name T36
Test name
Test status
Simulation time 29705142 ps
CPU time 0.6 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 194952 kb
Host smart-a8d0b2fa-cf7f-40cc-b523-ca3963880ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511696420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1511696420
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3723471980
Short name T187
Test name
Test status
Simulation time 73130495 ps
CPU time 0.8 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 196276 kb
Host smart-bdad40fb-ea58-4b6c-93bf-d8c5b153c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723471980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3723471980
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1245221434
Short name T314
Test name
Test status
Simulation time 518307586 ps
CPU time 26.87 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 196624 kb
Host smart-194b079c-812e-493d-9858-c58e5cd951c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245221434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1245221434
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1724417567
Short name T509
Test name
Test status
Simulation time 85231368 ps
CPU time 1.06 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 196824 kb
Host smart-0beedddb-b76b-4cad-b24c-4bffdb316fdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724417567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1724417567
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.580543026
Short name T329
Test name
Test status
Simulation time 294044139 ps
CPU time 1.24 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 197348 kb
Host smart-417d746b-845d-4eb2-8ae1-be9d3dc6398e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580543026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.580543026
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3185045094
Short name T452
Test name
Test status
Simulation time 479310624 ps
CPU time 1.74 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 196644 kb
Host smart-46ad56d2-3cbf-449f-89c8-b2c5d3bdf344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185045094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3185045094
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1806870094
Short name T218
Test name
Test status
Simulation time 97745253 ps
CPU time 0.99 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 195900 kb
Host smart-361a59c1-0d5b-4503-a512-095219224b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806870094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1806870094
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3182271415
Short name T193
Test name
Test status
Simulation time 41035602 ps
CPU time 1.04 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 196132 kb
Host smart-6be1ce05-4e21-4ed6-84f5-417064eb8d48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182271415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3182271415
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.395410426
Short name T268
Test name
Test status
Simulation time 132734190 ps
CPU time 3.07 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 198156 kb
Host smart-30f1ab95-a56f-4b15-85f8-9622e14913b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395410426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.395410426
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.228927538
Short name T192
Test name
Test status
Simulation time 29387669 ps
CPU time 0.91 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:22 PM PDT 24
Peak memory 196640 kb
Host smart-dd927c65-ddc3-471a-b6d5-d2faa0916821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228927538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.228927538
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2427350947
Short name T649
Test name
Test status
Simulation time 61139143 ps
CPU time 1.06 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 195976 kb
Host smart-a857eda5-bdab-44d4-9f26-887b8ea53558
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427350947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2427350947
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3704488439
Short name T470
Test name
Test status
Simulation time 15542568601 ps
CPU time 191.55 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:14:41 PM PDT 24
Peak memory 198332 kb
Host smart-865830bc-b09d-4eb3-8011-6582b5233ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704488439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3704488439
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.674993055
Short name T408
Test name
Test status
Simulation time 31463852 ps
CPU time 0.57 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 194048 kb
Host smart-f3bfdd30-173f-4af8-9b98-faedf0193aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674993055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.674993055
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4181724251
Short name T691
Test name
Test status
Simulation time 89357992 ps
CPU time 0.72 seconds
Started Aug 16 05:11:30 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 195420 kb
Host smart-2b222fdb-5abd-4087-98a9-57b46699fe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181724251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4181724251
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3795284595
Short name T388
Test name
Test status
Simulation time 2327337921 ps
CPU time 11.65 seconds
Started Aug 16 05:11:22 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 196536 kb
Host smart-5e9252a9-8d42-497a-8239-1692e84561a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795284595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3795284595
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3573473080
Short name T484
Test name
Test status
Simulation time 31609560 ps
CPU time 0.69 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 195616 kb
Host smart-2d70caa5-b6bd-4d9e-b6cf-e3deac5ac83a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573473080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3573473080
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1660662125
Short name T167
Test name
Test status
Simulation time 176893570 ps
CPU time 0.92 seconds
Started Aug 16 05:11:24 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 195960 kb
Host smart-2564e2ad-5f21-4cc2-9c4e-3cc72de5be8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660662125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1660662125
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2917644240
Short name T579
Test name
Test status
Simulation time 58990674 ps
CPU time 2.33 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:18 PM PDT 24
Peak memory 198208 kb
Host smart-33472594-f0b6-4925-a287-42874236b887
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917644240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2917644240
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1409614530
Short name T118
Test name
Test status
Simulation time 442341457 ps
CPU time 2.69 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 196652 kb
Host smart-d6503cd3-ddae-4451-89b2-76aefb330f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409614530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1409614530
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2969423684
Short name T520
Test name
Test status
Simulation time 36912232 ps
CPU time 1.16 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 197260 kb
Host smart-54b4ac4d-2daf-482c-aa48-4442728337df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969423684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2969423684
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2984472376
Short name T546
Test name
Test status
Simulation time 69914198 ps
CPU time 0.7 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 194416 kb
Host smart-277038d6-98fb-41a9-99be-f25e40c53cae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984472376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2984472376
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1481216935
Short name T373
Test name
Test status
Simulation time 101954640 ps
CPU time 4.38 seconds
Started Aug 16 05:11:18 PM PDT 24
Finished Aug 16 05:11:23 PM PDT 24
Peak memory 198060 kb
Host smart-f822e1ef-8e4f-4dc9-a70e-25faad8d5995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481216935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1481216935
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.391977535
Short name T174
Test name
Test status
Simulation time 189187301 ps
CPU time 0.91 seconds
Started Aug 16 05:11:19 PM PDT 24
Finished Aug 16 05:11:20 PM PDT 24
Peak memory 195672 kb
Host smart-b382816a-68c6-4301-b988-6a4dc9a9eeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391977535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.391977535
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2828260917
Short name T240
Test name
Test status
Simulation time 158497382 ps
CPU time 1.21 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 195864 kb
Host smart-789e6377-fb15-4565-b20d-3a5d376d9862
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828260917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2828260917
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.150046653
Short name T657
Test name
Test status
Simulation time 25862927603 ps
CPU time 169.09 seconds
Started Aug 16 05:11:22 PM PDT 24
Finished Aug 16 05:14:11 PM PDT 24
Peak memory 198316 kb
Host smart-2acc22de-5682-4fbc-907a-7822ab0c4906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150046653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.150046653
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1687426221
Short name T435
Test name
Test status
Simulation time 13512098 ps
CPU time 0.57 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 194044 kb
Host smart-47b063e8-8152-48f9-b417-a9bded4a377c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687426221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1687426221
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1857490883
Short name T360
Test name
Test status
Simulation time 40722733 ps
CPU time 0.69 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 194136 kb
Host smart-01e307a9-7202-4b01-a1ce-ab3f442ada17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857490883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1857490883
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2006495007
Short name T326
Test name
Test status
Simulation time 3487688901 ps
CPU time 27.75 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:49 PM PDT 24
Peak memory 198304 kb
Host smart-35d160b0-db22-409a-9cfd-1c027127b608
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006495007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2006495007
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3386304382
Short name T548
Test name
Test status
Simulation time 33482272 ps
CPU time 0.72 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 195824 kb
Host smart-9bb55805-e72b-4b7d-a311-9f38fb047934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386304382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3386304382
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1111383067
Short name T567
Test name
Test status
Simulation time 130755593 ps
CPU time 1.11 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 196188 kb
Host smart-86271e9c-04c1-47ad-acd6-532a978b0abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111383067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1111383067
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3625638762
Short name T257
Test name
Test status
Simulation time 65182758 ps
CPU time 2.7 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 198196 kb
Host smart-51682f89-9be1-4454-9e6c-e2ce00d2cf5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625638762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3625638762
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3615561118
Short name T572
Test name
Test status
Simulation time 114576512 ps
CPU time 3.55 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 197240 kb
Host smart-60465a11-e989-4c06-ba82-a86fef30bf10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615561118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3615561118
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2509208105
Short name T296
Test name
Test status
Simulation time 161134055 ps
CPU time 1.01 seconds
Started Aug 16 05:11:21 PM PDT 24
Finished Aug 16 05:11:22 PM PDT 24
Peak memory 196224 kb
Host smart-2ab9ddf6-7d3e-454c-8579-c51ece887188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509208105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2509208105
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1094227584
Short name T707
Test name
Test status
Simulation time 291010280 ps
CPU time 1.03 seconds
Started Aug 16 05:11:19 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 196904 kb
Host smart-c43657ea-0293-499d-ada5-46deccffb2c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094227584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1094227584
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3555433361
Short name T592
Test name
Test status
Simulation time 1021570958 ps
CPU time 4.62 seconds
Started Aug 16 05:11:16 PM PDT 24
Finished Aug 16 05:11:21 PM PDT 24
Peak memory 198148 kb
Host smart-47bd8ae8-b0ac-4f93-8f99-c617fdffb8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555433361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3555433361
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3964537188
Short name T269
Test name
Test status
Simulation time 82406309 ps
CPU time 1.19 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 197016 kb
Host smart-232235bf-6399-4b36-8de1-247e3ffe8ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964537188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3964537188
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3016869445
Short name T595
Test name
Test status
Simulation time 94211992 ps
CPU time 1.27 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 198208 kb
Host smart-69f44041-7082-4bc9-b68b-d935d8b5a81e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016869445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3016869445
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1128287690
Short name T528
Test name
Test status
Simulation time 9544713260 ps
CPU time 22.73 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 198360 kb
Host smart-5ed6772d-28cc-4084-999a-3a5508a2c749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128287690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1128287690
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.838589601
Short name T313
Test name
Test status
Simulation time 22385819 ps
CPU time 0.63 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 194252 kb
Host smart-e1292d74-0993-4ef2-984b-9f0c550a6181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838589601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.838589601
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3157937312
Short name T506
Test name
Test status
Simulation time 41163860 ps
CPU time 0.8 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 195508 kb
Host smart-92570df4-d19f-4f0c-8e0a-0a33e00b3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157937312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3157937312
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1955280878
Short name T144
Test name
Test status
Simulation time 3334193896 ps
CPU time 28.49 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:55 PM PDT 24
Peak memory 197244 kb
Host smart-d7493a96-44be-41b2-9942-20dda3f92d56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955280878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1955280878
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.189878805
Short name T344
Test name
Test status
Simulation time 67707009 ps
CPU time 0.76 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 195896 kb
Host smart-f9b510cb-eb6f-46d1-95ab-23fcc43c2ab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189878805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.189878805
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3217294162
Short name T495
Test name
Test status
Simulation time 161400944 ps
CPU time 1.24 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:22 PM PDT 24
Peak memory 196124 kb
Host smart-c2c4931d-375a-4ac9-bcef-048bee4c3d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217294162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3217294162
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2039444722
Short name T587
Test name
Test status
Simulation time 79790981 ps
CPU time 2.99 seconds
Started Aug 16 05:11:20 PM PDT 24
Finished Aug 16 05:11:24 PM PDT 24
Peak memory 196428 kb
Host smart-2a07fc0a-d64d-4f90-8ef3-3386643c9325
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039444722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2039444722
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.675984777
Short name T566
Test name
Test status
Simulation time 1974634282 ps
CPU time 2.98 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 195960 kb
Host smart-9aab2ea3-cf68-47fb-88c8-123c2faefde8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675984777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
675984777
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.690287128
Short name T693
Test name
Test status
Simulation time 156797767 ps
CPU time 1.12 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 197240 kb
Host smart-47e4ce18-1628-4eea-b57c-04f52652828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690287128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.690287128
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4029320112
Short name T637
Test name
Test status
Simulation time 71099726 ps
CPU time 0.66 seconds
Started Aug 16 05:11:24 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 195048 kb
Host smart-190229d8-c39e-44a6-b665-9e8f0eb4c35f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029320112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4029320112
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.125778492
Short name T464
Test name
Test status
Simulation time 249154059 ps
CPU time 4.23 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 198076 kb
Host smart-3f3dcf44-de6c-45d5-af80-479c39d1b374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125778492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.125778492
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3494515749
Short name T111
Test name
Test status
Simulation time 157745470 ps
CPU time 0.87 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 196280 kb
Host smart-c76096f0-742a-45eb-b7d5-de984b0bc31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494515749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3494515749
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3771609733
Short name T356
Test name
Test status
Simulation time 336227292 ps
CPU time 1.32 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 196824 kb
Host smart-acb4e481-27fb-4718-809c-9dc5309b3fe3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771609733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3771609733
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1198146309
Short name T3
Test name
Test status
Simulation time 21555571980 ps
CPU time 124.72 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:13:30 PM PDT 24
Peak memory 198324 kb
Host smart-47f401d0-998d-420b-8826-dda64ce4ef8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198146309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1198146309
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3131249808
Short name T547
Test name
Test status
Simulation time 21150831 ps
CPU time 0.56 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 193960 kb
Host smart-e166cdb3-63ef-4cf5-92ec-5ba372633a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131249808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3131249808
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3525004799
Short name T583
Test name
Test status
Simulation time 23235833 ps
CPU time 0.62 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 194068 kb
Host smart-3a03d0c3-353b-4a92-9d9e-276fbcceb8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525004799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3525004799
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.90178960
Short name T151
Test name
Test status
Simulation time 3645291227 ps
CPU time 27.14 seconds
Started Aug 16 05:11:24 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 198324 kb
Host smart-41217c2c-85ef-48b4-8524-66036d4474b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90178960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.90178960
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2865962749
Short name T131
Test name
Test status
Simulation time 22161929 ps
CPU time 0.61 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 195232 kb
Host smart-73ac78ad-2fbe-4434-a8cd-b227a1bfb186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865962749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2865962749
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.850564287
Short name T421
Test name
Test status
Simulation time 57726881 ps
CPU time 0.96 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 195976 kb
Host smart-9747fd9d-23b8-46a3-97f3-53c0b4b46848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850564287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.850564287
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.581569848
Short name T331
Test name
Test status
Simulation time 314806093 ps
CPU time 3 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 198140 kb
Host smart-a738ea52-566d-4716-95a3-76fc2121c7c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581569848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.581569848
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1314473631
Short name T207
Test name
Test status
Simulation time 152643319 ps
CPU time 2.92 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 198200 kb
Host smart-c9ca8538-3d1a-496c-86f5-84b40b6f6b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314473631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1314473631
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1950390899
Short name T191
Test name
Test status
Simulation time 40111685 ps
CPU time 0.99 seconds
Started Aug 16 05:11:23 PM PDT 24
Finished Aug 16 05:11:25 PM PDT 24
Peak memory 195884 kb
Host smart-8828da05-438d-497a-99fd-a5d54b208cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950390899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1950390899
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4042563365
Short name T440
Test name
Test status
Simulation time 66026992 ps
CPU time 0.81 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 196552 kb
Host smart-895cbc91-2c56-4dd2-a250-19a596342e04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042563365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4042563365
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3103419721
Short name T170
Test name
Test status
Simulation time 174102082 ps
CPU time 2.82 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:40 PM PDT 24
Peak memory 197972 kb
Host smart-25236b48-ccdb-46d1-92cb-c2f01f702a25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103419721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3103419721
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3053598101
Short name T578
Test name
Test status
Simulation time 40326256 ps
CPU time 1.13 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 196704 kb
Host smart-ab8ab98b-39a2-49c6-b0c3-e73d1dd334bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053598101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3053598101
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2146576345
Short name T304
Test name
Test status
Simulation time 28150774 ps
CPU time 0.95 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 196576 kb
Host smart-6859dd5d-48a9-4d6c-93a6-7fd391f582e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146576345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2146576345
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1617740422
Short name T606
Test name
Test status
Simulation time 2577582137 ps
CPU time 36.75 seconds
Started Aug 16 05:11:39 PM PDT 24
Finished Aug 16 05:12:16 PM PDT 24
Peak memory 198324 kb
Host smart-0be58184-1b5c-4e79-9212-31faa460867d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617740422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1617740422
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1645738579
Short name T251
Test name
Test status
Simulation time 39367295 ps
CPU time 0.56 seconds
Started Aug 16 05:11:25 PM PDT 24
Finished Aug 16 05:11:26 PM PDT 24
Peak memory 195060 kb
Host smart-7afa5eff-0e4a-4452-a4be-cb350f793583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645738579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1645738579
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.939998073
Short name T163
Test name
Test status
Simulation time 44068541 ps
CPU time 0.84 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 196100 kb
Host smart-74af764a-4417-46e6-964f-958693ce46a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939998073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.939998073
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.357563765
Short name T305
Test name
Test status
Simulation time 199222939 ps
CPU time 9.21 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 196796 kb
Host smart-f4ed54aa-1192-4e56-8c50-48e9e32d54c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357563765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.357563765
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.140612681
Short name T671
Test name
Test status
Simulation time 236275439 ps
CPU time 0.87 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 197224 kb
Host smart-02c65f16-45a8-452d-b0e6-70d3f5a4c917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140612681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.140612681
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2508343870
Short name T97
Test name
Test status
Simulation time 86134038 ps
CPU time 1.24 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 195908 kb
Host smart-1f64ce99-6e6a-42cb-a0cb-9879bed9588e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508343870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2508343870
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1662255937
Short name T141
Test name
Test status
Simulation time 330200147 ps
CPU time 3.29 seconds
Started Aug 16 05:11:30 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 198116 kb
Host smart-96235534-81b8-4d83-85f9-a5ab491f49f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662255937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1662255937
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1818201339
Short name T379
Test name
Test status
Simulation time 154277413 ps
CPU time 2.13 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 197220 kb
Host smart-8ebdee7e-b28f-42be-bdbe-64b23301461a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818201339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1818201339
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.722538261
Short name T683
Test name
Test status
Simulation time 23057741 ps
CPU time 0.75 seconds
Started Aug 16 05:11:33 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 195416 kb
Host smart-4541d05a-90e1-4f6d-9f57-871cf8d183c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722538261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.722538261
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1820937083
Short name T488
Test name
Test status
Simulation time 31633209 ps
CPU time 0.66 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 194364 kb
Host smart-6d0ad9f3-06c0-483d-9fe3-0e7d6c53d137
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820937083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1820937083
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2944824875
Short name T175
Test name
Test status
Simulation time 2814727592 ps
CPU time 5.89 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 198224 kb
Host smart-8c904e80-3cac-4f14-b6c2-d81a121ea23b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944824875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2944824875
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1611957351
Short name T648
Test name
Test status
Simulation time 161851410 ps
CPU time 0.85 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 196176 kb
Host smart-59f3064f-50b3-4af2-9996-a8ca28ad6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611957351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1611957351
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2124527079
Short name T508
Test name
Test status
Simulation time 90390267 ps
CPU time 0.83 seconds
Started Aug 16 05:11:34 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 195292 kb
Host smart-b28f288d-1eb3-457e-8521-7f3d67d6074c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124527079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2124527079
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3504480507
Short name T702
Test name
Test status
Simulation time 38979508795 ps
CPU time 31.48 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:58 PM PDT 24
Peak memory 198348 kb
Host smart-222a5ca8-f4fa-491f-af77-f1f6c1914b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504480507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3504480507
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2517307932
Short name T454
Test name
Test status
Simulation time 136904904 ps
CPU time 0.54 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 194040 kb
Host smart-a8988e27-eaf3-4e9d-bfad-faf51c95975b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517307932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2517307932
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1457928358
Short name T632
Test name
Test status
Simulation time 88911412 ps
CPU time 0.77 seconds
Started Aug 16 05:11:30 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 195640 kb
Host smart-e0d5f4d5-401c-465f-b26b-e06c43ed233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457928358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1457928358
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1045968299
Short name T537
Test name
Test status
Simulation time 254085347 ps
CPU time 12.3 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:44 PM PDT 24
Peak memory 195608 kb
Host smart-c40704cf-1978-4f6d-8dd3-8e5b4b6fe02b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045968299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1045968299
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1946262491
Short name T16
Test name
Test status
Simulation time 240748276 ps
CPU time 0.99 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 196476 kb
Host smart-58aca690-1556-4a21-83ce-fdf8dfeb050e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946262491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1946262491
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3774498515
Short name T564
Test name
Test status
Simulation time 167569042 ps
CPU time 1.22 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 196756 kb
Host smart-1e3ef739-d185-4362-b2ea-516035f7a84e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774498515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3774498515
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.873510951
Short name T203
Test name
Test status
Simulation time 26983802 ps
CPU time 1.11 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 197144 kb
Host smart-9e1c6b31-35fc-459a-a340-5ef83deef670
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873510951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.873510951
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1888769887
Short name T153
Test name
Test status
Simulation time 292587654 ps
CPU time 3.26 seconds
Started Aug 16 05:11:42 PM PDT 24
Finished Aug 16 05:11:46 PM PDT 24
Peak memory 197308 kb
Host smart-1f7c6e45-0f5f-45ab-8a24-0e5c4165c2b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888769887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1888769887
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3074176755
Short name T472
Test name
Test status
Simulation time 29619698 ps
CPU time 0.99 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 196208 kb
Host smart-899cd8ba-b9b3-46ce-913a-8434686ae4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074176755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3074176755
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1118022416
Short name T420
Test name
Test status
Simulation time 43113044 ps
CPU time 0.68 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 196212 kb
Host smart-89caafdf-51ca-4399-80cc-52d0bbf39a31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118022416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1118022416
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2532738455
Short name T25
Test name
Test status
Simulation time 121827748 ps
CPU time 4.99 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 198096 kb
Host smart-5d4d9192-6b42-420d-91d0-8558ec98c031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532738455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2532738455
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4246678166
Short name T493
Test name
Test status
Simulation time 138490638 ps
CPU time 1.13 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 196408 kb
Host smart-15dbf6ff-ff06-4381-b6ee-62a41e4a3de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246678166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4246678166
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2711973810
Short name T156
Test name
Test status
Simulation time 146227901 ps
CPU time 0.89 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 196432 kb
Host smart-dc322b6b-acaa-40b8-9438-86cecd70ce9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711973810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2711973810
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4236546629
Short name T274
Test name
Test status
Simulation time 10000087325 ps
CPU time 170.12 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:14:18 PM PDT 24
Peak memory 198236 kb
Host smart-c58561e6-9b2b-4f1f-9252-86b2a9e962a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236546629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4236546629
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3996549939
Short name T60
Test name
Test status
Simulation time 9828883316 ps
CPU time 33.8 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:12:14 PM PDT 24
Peak memory 198500 kb
Host smart-53a05434-faa7-465e-a5fa-f76bac88931e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3996549939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3996549939
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1853723638
Short name T688
Test name
Test status
Simulation time 42672222 ps
CPU time 0.6 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 194228 kb
Host smart-e5f0e39c-facf-4a73-a099-e8aa43127e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853723638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1853723638
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.492742224
Short name T208
Test name
Test status
Simulation time 91188895 ps
CPU time 0.91 seconds
Started Aug 16 05:10:08 PM PDT 24
Finished Aug 16 05:10:10 PM PDT 24
Peak memory 196104 kb
Host smart-10a7d1c5-c534-4668-ad23-5dbb8c5fcbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492742224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.492742224
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1607763448
Short name T397
Test name
Test status
Simulation time 1866943951 ps
CPU time 26.87 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:55 PM PDT 24
Peak memory 198144 kb
Host smart-684506d3-4189-4076-b1c5-12a4ac2c77fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607763448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1607763448
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2486620975
Short name T532
Test name
Test status
Simulation time 72037029 ps
CPU time 1.1 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196888 kb
Host smart-4cdd6d9b-7c44-4ce4-92ad-a3bb3e226142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486620975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2486620975
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1322547456
Short name T645
Test name
Test status
Simulation time 124542040 ps
CPU time 0.91 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 195968 kb
Host smart-2a3ca02a-6e12-4216-8959-81ee9049332a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322547456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1322547456
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3228363574
Short name T310
Test name
Test status
Simulation time 126983689 ps
CPU time 1.43 seconds
Started Aug 16 05:10:21 PM PDT 24
Finished Aug 16 05:10:23 PM PDT 24
Peak memory 196684 kb
Host smart-dae817ac-37dc-46c3-8624-d1e06a6bfef2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228363574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3228363574
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1791468067
Short name T278
Test name
Test status
Simulation time 76135319 ps
CPU time 2.3 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 197360 kb
Host smart-5f7b7286-cdc3-4660-b03c-956c06951ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791468067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1791468067
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1760680859
Short name T598
Test name
Test status
Simulation time 64815316 ps
CPU time 1.23 seconds
Started Aug 16 05:10:13 PM PDT 24
Finished Aug 16 05:10:15 PM PDT 24
Peak memory 196000 kb
Host smart-386da078-bcfd-464f-8d94-ba7cb5f630cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760680859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1760680859
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.4065122255
Short name T104
Test name
Test status
Simulation time 363031607 ps
CPU time 1.05 seconds
Started Aug 16 05:10:21 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 196164 kb
Host smart-59fbb65f-acb1-4f13-9533-317e0ac86915
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065122255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.4065122255
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1615170815
Short name T5
Test name
Test status
Simulation time 542137434 ps
CPU time 3.31 seconds
Started Aug 16 05:10:18 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 196388 kb
Host smart-7fe42774-df4c-44ce-ab8d-7c93fb494fb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615170815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1615170815
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1853679392
Short name T46
Test name
Test status
Simulation time 92021939 ps
CPU time 0.87 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 213964 kb
Host smart-a8c58fb6-ee92-4499-a236-083a370006fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853679392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1853679392
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.973599883
Short name T182
Test name
Test status
Simulation time 1138826063 ps
CPU time 1.48 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:28 PM PDT 24
Peak memory 195672 kb
Host smart-22708b65-a234-41b1-9028-f17feb7f2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973599883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.973599883
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1107034131
Short name T448
Test name
Test status
Simulation time 41688316 ps
CPU time 0.89 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 195424 kb
Host smart-4aef061a-d8ca-44ed-930f-1348f8a18777
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107034131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1107034131
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3209411883
Short name T423
Test name
Test status
Simulation time 5809458440 ps
CPU time 76.72 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 198336 kb
Host smart-60db89eb-4def-4938-9dfd-c90fd12bc1f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209411883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3209411883
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.750033200
Short name T169
Test name
Test status
Simulation time 11529910 ps
CPU time 0.57 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:27 PM PDT 24
Peak memory 194048 kb
Host smart-b9df10e9-f895-4297-ba65-1a3998bbc88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750033200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.750033200
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2054384368
Short name T366
Test name
Test status
Simulation time 15593611 ps
CPU time 0.65 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 194124 kb
Host smart-900a7cca-cbbd-45df-9239-e3121b66d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054384368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2054384368
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.474157217
Short name T619
Test name
Test status
Simulation time 420130865 ps
CPU time 6.05 seconds
Started Aug 16 05:11:24 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 196944 kb
Host smart-cc71fd0a-189a-4ff3-a0e1-77fb2cef97f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474157217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.474157217
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1028269923
Short name T550
Test name
Test status
Simulation time 87965746 ps
CPU time 1.16 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 196804 kb
Host smart-bf1073c7-15d3-47fe-b04e-1fb25fce9156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028269923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1028269923
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3510401898
Short name T221
Test name
Test status
Simulation time 166344198 ps
CPU time 1.23 seconds
Started Aug 16 05:11:34 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 196700 kb
Host smart-2fd1298c-5f7b-4956-a0cc-91940055c93f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510401898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3510401898
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2910646773
Short name T442
Test name
Test status
Simulation time 39351156 ps
CPU time 1.46 seconds
Started Aug 16 05:11:30 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 196708 kb
Host smart-46697931-5bf8-4bcb-9aea-0f68a6b7a1ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910646773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2910646773
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4216484192
Short name T433
Test name
Test status
Simulation time 31094504 ps
CPU time 0.93 seconds
Started Aug 16 05:11:50 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 195728 kb
Host smart-74d60035-3c67-4f84-9752-42d54e70483c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216484192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4216484192
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1091476570
Short name T621
Test name
Test status
Simulation time 52207503 ps
CPU time 1.04 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 196740 kb
Host smart-47d3cc2b-9c0a-498f-8f4d-b8f26eef549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091476570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1091476570
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3980073662
Short name T281
Test name
Test status
Simulation time 47406506 ps
CPU time 1.1 seconds
Started Aug 16 05:11:30 PM PDT 24
Finished Aug 16 05:11:31 PM PDT 24
Peak memory 195976 kb
Host smart-c92e3beb-0306-445d-a6e6-e3e3adfc9e89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980073662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3980073662
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1262696747
Short name T320
Test name
Test status
Simulation time 197704259 ps
CPU time 2.8 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 198124 kb
Host smart-4de311ef-ce75-4638-9197-7cc38c5342d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262696747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1262696747
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.228998310
Short name T417
Test name
Test status
Simulation time 198726429 ps
CPU time 1.27 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 196396 kb
Host smart-7d521473-74c6-4d7b-a137-8ba432c4ea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228998310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.228998310
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3951889069
Short name T623
Test name
Test status
Simulation time 230578964 ps
CPU time 1 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 195840 kb
Host smart-817ab06b-4f7e-40cf-8654-7ea6f5e37ea6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951889069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3951889069
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2130669057
Short name T350
Test name
Test status
Simulation time 2531931593 ps
CPU time 33.11 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 198288 kb
Host smart-1b43f733-5feb-4560-905f-c1f9d1d487e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130669057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2130669057
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1633733069
Short name T697
Test name
Test status
Simulation time 11253893 ps
CPU time 0.53 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 194032 kb
Host smart-4f3a0c83-d7c8-43fa-bde8-ac4a0425c602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633733069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1633733069
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.72811754
Short name T512
Test name
Test status
Simulation time 27966940 ps
CPU time 0.63 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 193924 kb
Host smart-affbf892-dd3e-4e6a-ac2f-2ad1489808c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72811754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.72811754
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.105561871
Short name T132
Test name
Test status
Simulation time 1360044380 ps
CPU time 17.99 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:55 PM PDT 24
Peak memory 196436 kb
Host smart-b38fe480-dbb9-4ccc-9452-eb2ac258756f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105561871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.105561871
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.235462584
Short name T211
Test name
Test status
Simulation time 162427633 ps
CPU time 0.88 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 197876 kb
Host smart-bd97337b-3139-426f-9c03-b52e4b3a1a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235462584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.235462584
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1026938168
Short name T591
Test name
Test status
Simulation time 98336126 ps
CPU time 1.25 seconds
Started Aug 16 05:11:28 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 197016 kb
Host smart-41faa822-0c14-4163-903e-ac4b957c7215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026938168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1026938168
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1575841166
Short name T130
Test name
Test status
Simulation time 78717844 ps
CPU time 3.17 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 198280 kb
Host smart-afd5ecbd-d2a0-4bf7-a3b1-75ffad5eb3e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575841166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1575841166
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2229388647
Short name T252
Test name
Test status
Simulation time 46165475 ps
CPU time 0.93 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 195716 kb
Host smart-b7298073-b074-49fb-9595-11a8c9825c23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229388647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2229388647
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1783656715
Short name T609
Test name
Test status
Simulation time 66216721 ps
CPU time 1.11 seconds
Started Aug 16 05:11:57 PM PDT 24
Finished Aug 16 05:11:58 PM PDT 24
Peak memory 197152 kb
Host smart-b3aec582-5b4a-47ae-ba5f-809058861b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783656715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1783656715
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1557713700
Short name T399
Test name
Test status
Simulation time 140877364 ps
CPU time 1.22 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:29 PM PDT 24
Peak memory 198132 kb
Host smart-115d11e6-6bcc-43cb-a00f-fff8dc0c5bda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557713700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1557713700
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4140382471
Short name T674
Test name
Test status
Simulation time 700295867 ps
CPU time 2.98 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 198132 kb
Host smart-f1375c78-3b98-41c1-82f6-ee0d347358b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140382471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4140382471
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3862645340
Short name T456
Test name
Test status
Simulation time 225827760 ps
CPU time 1.15 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 196736 kb
Host smart-c46eb4ad-4c7e-460a-8df9-5f9c83b563bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862645340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3862645340
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4151348705
Short name T620
Test name
Test status
Simulation time 132247598 ps
CPU time 1.11 seconds
Started Aug 16 05:11:27 PM PDT 24
Finished Aug 16 05:11:28 PM PDT 24
Peak memory 196544 kb
Host smart-b92b825b-ea9e-4263-bf7e-e7af500b2a6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151348705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4151348705
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3891120714
Short name T9
Test name
Test status
Simulation time 32441709095 ps
CPU time 111.24 seconds
Started Aug 16 05:11:29 PM PDT 24
Finished Aug 16 05:13:21 PM PDT 24
Peak memory 198356 kb
Host smart-6d9bb6da-89fd-4c2e-a498-3c707e4278c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891120714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3891120714
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1354095985
Short name T342
Test name
Test status
Simulation time 22659273 ps
CPU time 0.56 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 194008 kb
Host smart-a22b2c36-b087-414b-a202-b818c72acafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354095985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1354095985
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2050334533
Short name T477
Test name
Test status
Simulation time 27321267 ps
CPU time 0.8 seconds
Started Aug 16 05:11:57 PM PDT 24
Finished Aug 16 05:11:58 PM PDT 24
Peak memory 196432 kb
Host smart-a9ed919e-972f-4717-9076-43a47f8f11f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050334533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2050334533
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1079643942
Short name T157
Test name
Test status
Simulation time 3412221769 ps
CPU time 25.87 seconds
Started Aug 16 05:11:33 PM PDT 24
Finished Aug 16 05:11:59 PM PDT 24
Peak memory 198308 kb
Host smart-0c1ee2ca-1feb-4e29-b982-ed175623c588
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079643942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1079643942
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4080286122
Short name T322
Test name
Test status
Simulation time 31869025 ps
CPU time 0.67 seconds
Started Aug 16 05:11:50 PM PDT 24
Finished Aug 16 05:11:50 PM PDT 24
Peak memory 194804 kb
Host smart-78b2f76a-a135-4cf9-9ee3-3cbdcf72762c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080286122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4080286122
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1089349434
Short name T374
Test name
Test status
Simulation time 142064573 ps
CPU time 1.05 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 195956 kb
Host smart-667adc97-20d0-41b0-bbc1-9c9c1658d8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089349434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1089349434
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3013163851
Short name T401
Test name
Test status
Simulation time 193283104 ps
CPU time 2 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 198220 kb
Host smart-6587c072-97b9-4efe-8f81-7245c989e23f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013163851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3013163851
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.835792319
Short name T444
Test name
Test status
Simulation time 135009010 ps
CPU time 2.91 seconds
Started Aug 16 05:11:26 PM PDT 24
Finished Aug 16 05:11:30 PM PDT 24
Peak memory 198224 kb
Host smart-3d0bc49a-a6ca-46d9-9ff6-9f84b7ddad72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835792319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
835792319
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2233462846
Short name T385
Test name
Test status
Simulation time 50676894 ps
CPU time 1.08 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 196900 kb
Host smart-c51f2c4c-b92e-499e-bcd6-02302d603714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233462846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2233462846
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1844458226
Short name T631
Test name
Test status
Simulation time 107876241 ps
CPU time 0.85 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 196720 kb
Host smart-b9b2bc95-72e8-4974-a8ef-1fb5c58e8aa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844458226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1844458226
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2152990151
Short name T219
Test name
Test status
Simulation time 221129677 ps
CPU time 5.43 seconds
Started Aug 16 05:11:33 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 198108 kb
Host smart-bb1896a2-30df-420d-9971-60758747d323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152990151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2152990151
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3991366868
Short name T162
Test name
Test status
Simulation time 237220448 ps
CPU time 1.08 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 195680 kb
Host smart-69c8b987-975a-441d-9f29-e096e8bc575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991366868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3991366868
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1546562619
Short name T13
Test name
Test status
Simulation time 98343999 ps
CPU time 1.43 seconds
Started Aug 16 05:11:39 PM PDT 24
Finished Aug 16 05:11:40 PM PDT 24
Peak memory 198192 kb
Host smart-ed6f9067-2c7c-4c66-9bbc-ccd686ae0888
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546562619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1546562619
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3828477985
Short name T349
Test name
Test status
Simulation time 35945530761 ps
CPU time 84.71 seconds
Started Aug 16 05:11:32 PM PDT 24
Finished Aug 16 05:12:57 PM PDT 24
Peak memory 198296 kb
Host smart-99e0878b-18f1-464c-98b0-96cc82cf6187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828477985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3828477985
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.250255636
Short name T491
Test name
Test status
Simulation time 31052441 ps
CPU time 0.59 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 194044 kb
Host smart-58862b1b-6265-4c58-aa4e-64769c8b980a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250255636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.250255636
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3435576018
Short name T439
Test name
Test status
Simulation time 46881784 ps
CPU time 0.82 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 195484 kb
Host smart-8ff5f45b-15e2-4991-b91a-966f50a2fe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435576018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3435576018
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4109253614
Short name T222
Test name
Test status
Simulation time 1601022823 ps
CPU time 14.92 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:53 PM PDT 24
Peak memory 196584 kb
Host smart-77ee39d0-d832-478e-962e-b87622d94b86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109253614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4109253614
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3771675672
Short name T22
Test name
Test status
Simulation time 25050743 ps
CPU time 0.66 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 195480 kb
Host smart-2081a100-5af4-4c64-b921-63f062a0d75a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771675672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3771675672
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.312206152
Short name T202
Test name
Test status
Simulation time 184245080 ps
CPU time 1.4 seconds
Started Aug 16 05:11:34 PM PDT 24
Finished Aug 16 05:11:35 PM PDT 24
Peak memory 196748 kb
Host smart-0fd5026a-b190-4dd2-84fd-9b2975c4ed74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312206152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.312206152
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3301085427
Short name T285
Test name
Test status
Simulation time 65022177 ps
CPU time 2.39 seconds
Started Aug 16 05:11:47 PM PDT 24
Finished Aug 16 05:11:55 PM PDT 24
Peak memory 198136 kb
Host smart-8c98ee26-b95a-46f7-86e3-911adcc485e7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301085427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3301085427
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2134559867
Short name T347
Test name
Test status
Simulation time 200771087 ps
CPU time 1.1 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 195860 kb
Host smart-d6aef015-933b-4f5c-a5ea-c300a60e555e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134559867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2134559867
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2863569289
Short name T500
Test name
Test status
Simulation time 17295741 ps
CPU time 0.71 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:01 PM PDT 24
Peak memory 196184 kb
Host smart-f611da9a-6f6a-49f2-89e4-8dd0a65dc2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863569289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2863569289
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2255230768
Short name T425
Test name
Test status
Simulation time 224149173 ps
CPU time 1.06 seconds
Started Aug 16 05:11:31 PM PDT 24
Finished Aug 16 05:11:32 PM PDT 24
Peak memory 195936 kb
Host smart-41f983f4-f888-4c1a-8598-3a467fe8312b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255230768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2255230768
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1112955344
Short name T340
Test name
Test status
Simulation time 268446512 ps
CPU time 4.07 seconds
Started Aug 16 05:11:34 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 198116 kb
Host smart-23eaa89c-3f12-44f1-aa06-81849b29c7bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112955344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1112955344
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4135936456
Short name T125
Test name
Test status
Simulation time 122837326 ps
CPU time 1.31 seconds
Started Aug 16 05:11:33 PM PDT 24
Finished Aug 16 05:11:34 PM PDT 24
Peak memory 198128 kb
Host smart-a3c8078e-7b75-4122-8f90-1887ab998c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135936456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4135936456
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2801432552
Short name T429
Test name
Test status
Simulation time 28981409 ps
CPU time 0.77 seconds
Started Aug 16 05:11:50 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 195368 kb
Host smart-7e6d55b8-fd84-4df7-9868-7cacb07ff49d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801432552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2801432552
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1883303633
Short name T120
Test name
Test status
Simulation time 7272282859 ps
CPU time 24.18 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 198404 kb
Host smart-eb53a168-625c-47ef-ba2b-6c24413a6d96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883303633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1883303633
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.622011873
Short name T676
Test name
Test status
Simulation time 1906017506 ps
CPU time 32.34 seconds
Started Aug 16 05:12:01 PM PDT 24
Finished Aug 16 05:12:34 PM PDT 24
Peak memory 197696 kb
Host smart-93ade177-4ba2-4bbd-831b-84b841aecf09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=622011873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.622011873
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3797190273
Short name T498
Test name
Test status
Simulation time 21495023 ps
CPU time 0.57 seconds
Started Aug 16 05:11:39 PM PDT 24
Finished Aug 16 05:11:40 PM PDT 24
Peak memory 193976 kb
Host smart-28e78c62-0d71-4bbd-8723-6410802b8179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797190273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3797190273
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2803957038
Short name T633
Test name
Test status
Simulation time 298147073 ps
CPU time 0.74 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 196168 kb
Host smart-9868eb5a-8e12-477b-8c74-aa19f02852ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803957038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2803957038
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.261840155
Short name T255
Test name
Test status
Simulation time 270373436 ps
CPU time 4.69 seconds
Started Aug 16 05:11:58 PM PDT 24
Finished Aug 16 05:12:03 PM PDT 24
Peak memory 196416 kb
Host smart-5bf9e9eb-eee8-4e00-b20d-9b9dcb52e508
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261840155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.261840155
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3889015297
Short name T21
Test name
Test status
Simulation time 128165073 ps
CPU time 0.64 seconds
Started Aug 16 05:11:42 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 194552 kb
Host smart-185d96ed-c08c-4089-a1eb-9d9d035f4469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889015297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3889015297
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3025978779
Short name T663
Test name
Test status
Simulation time 111051042 ps
CPU time 0.66 seconds
Started Aug 16 05:11:33 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 194464 kb
Host smart-ce4c0dae-15ae-4137-99f7-43193a877126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025978779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3025978779
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1748195851
Short name T244
Test name
Test status
Simulation time 29058128 ps
CPU time 1.09 seconds
Started Aug 16 05:11:50 PM PDT 24
Finished Aug 16 05:11:51 PM PDT 24
Peak memory 197136 kb
Host smart-f1b4b586-e6e4-4fee-aaed-31fd226e383a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748195851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1748195851
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3959350515
Short name T112
Test name
Test status
Simulation time 154442942 ps
CPU time 2.86 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 197196 kb
Host smart-7d3bd33b-97e0-42ad-bb54-4a812d967837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959350515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3959350515
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.111662945
Short name T706
Test name
Test status
Simulation time 385176935 ps
CPU time 1.13 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 196936 kb
Host smart-2324ac33-3ec2-481b-b714-2e6f6d275939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111662945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.111662945
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3441896331
Short name T555
Test name
Test status
Simulation time 158123175 ps
CPU time 0.87 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 196460 kb
Host smart-07d1cc6b-ec9a-41e8-93e8-8f7219366f0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441896331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3441896331
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2009975922
Short name T10
Test name
Test status
Simulation time 2241692562 ps
CPU time 2.67 seconds
Started Aug 16 05:12:12 PM PDT 24
Finished Aug 16 05:12:15 PM PDT 24
Peak memory 198076 kb
Host smart-da49a2ae-4edf-459a-971a-08e084262010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009975922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2009975922
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.742894405
Short name T246
Test name
Test status
Simulation time 168383605 ps
CPU time 0.82 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 195364 kb
Host smart-f7ad29dd-dd98-4c5f-af1a-70dd44726ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742894405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.742894405
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3236819808
Short name T511
Test name
Test status
Simulation time 342092403 ps
CPU time 1.34 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 196920 kb
Host smart-1e80477b-0471-4bac-9433-d05d2fd45700
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236819808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3236819808
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3904222204
Short name T309
Test name
Test status
Simulation time 88001728839 ps
CPU time 96.47 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:13:16 PM PDT 24
Peak memory 198372 kb
Host smart-de495858-a5f9-40c1-b919-85de6b206626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904222204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3904222204
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3816783267
Short name T471
Test name
Test status
Simulation time 21263174 ps
CPU time 0.57 seconds
Started Aug 16 05:11:51 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 194052 kb
Host smart-80bd5332-f282-4307-aaae-ab68b398318a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816783267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3816783267
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.35711085
Short name T389
Test name
Test status
Simulation time 27547569 ps
CPU time 0.77 seconds
Started Aug 16 05:11:39 PM PDT 24
Finished Aug 16 05:11:40 PM PDT 24
Peak memory 195980 kb
Host smart-c0969a91-a0b8-492b-a754-f23eae06c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35711085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.35711085
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2898959680
Short name T165
Test name
Test status
Simulation time 6464343108 ps
CPU time 11.3 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:17 PM PDT 24
Peak memory 197160 kb
Host smart-ff8b3e8d-8add-4cd8-b3af-14df2945f7bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898959680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2898959680
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2665931335
Short name T358
Test name
Test status
Simulation time 156867869 ps
CPU time 0.74 seconds
Started Aug 16 05:11:46 PM PDT 24
Finished Aug 16 05:11:47 PM PDT 24
Peak memory 195976 kb
Host smart-3aa2c258-e233-4819-b828-09e67af39c02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665931335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2665931335
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.723315593
Short name T154
Test name
Test status
Simulation time 127553766 ps
CPU time 1.08 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 196072 kb
Host smart-61232c08-e4df-4146-8e45-7dc8bf3a026e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723315593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.723315593
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2521555000
Short name T515
Test name
Test status
Simulation time 165490392 ps
CPU time 1.88 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:47 PM PDT 24
Peak memory 198096 kb
Host smart-0dbeb3e1-87f0-4be3-a63f-de0bd3bb43f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521555000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2521555000
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2361055207
Short name T134
Test name
Test status
Simulation time 54213454 ps
CPU time 0.99 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 195808 kb
Host smart-98dd1e05-aa0c-4bb0-85f2-563c5d180108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361055207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2361055207
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4032735745
Short name T51
Test name
Test status
Simulation time 90841225 ps
CPU time 0.98 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 196704 kb
Host smart-0d236c3c-eb38-4e36-aaad-e7e8630401f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032735745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4032735745
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.53877181
Short name T228
Test name
Test status
Simulation time 30392564 ps
CPU time 1.1 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 196276 kb
Host smart-4b5bc665-ad6f-41a6-9997-216a5a0b6c92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53877181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup_
pulldown.53877181
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1153904509
Short name T581
Test name
Test status
Simulation time 971964331 ps
CPU time 3.88 seconds
Started Aug 16 05:12:00 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 198116 kb
Host smart-25c84a07-4083-4c17-bc76-80af8f361170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153904509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1153904509
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1845625330
Short name T673
Test name
Test status
Simulation time 141554978 ps
CPU time 1.18 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 196580 kb
Host smart-02ae71a9-8f96-419d-9896-f95625fb8cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845625330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1845625330
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1038958889
Short name T336
Test name
Test status
Simulation time 872254054 ps
CPU time 1 seconds
Started Aug 16 05:11:45 PM PDT 24
Finished Aug 16 05:11:46 PM PDT 24
Peak memory 196528 kb
Host smart-9a7bfd84-9680-4b14-b910-210db0cfb62b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038958889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1038958889
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3592141892
Short name T527
Test name
Test status
Simulation time 31044326510 ps
CPU time 124.84 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:13:40 PM PDT 24
Peak memory 198496 kb
Host smart-40538861-c6b8-483a-bfb4-7fe24f9f3906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592141892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3592141892
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3900514648
Short name T361
Test name
Test status
Simulation time 52608765 ps
CPU time 0.56 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 194068 kb
Host smart-7035d9d5-508a-4f87-a1ad-d3bdee5cf675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900514648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3900514648
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2136762070
Short name T582
Test name
Test status
Simulation time 23073709 ps
CPU time 0.74 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:07 PM PDT 24
Peak memory 195264 kb
Host smart-32ee82d9-7434-48a4-891c-76b9d20e5089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136762070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2136762070
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1647393563
Short name T142
Test name
Test status
Simulation time 3604754674 ps
CPU time 24.69 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:12:01 PM PDT 24
Peak memory 197012 kb
Host smart-0d308faf-13a5-4db3-bf4f-106aef3d7b54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647393563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1647393563
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2407729824
Short name T359
Test name
Test status
Simulation time 45017956 ps
CPU time 0.64 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 194328 kb
Host smart-e11b3dc2-467e-472d-b1b8-785db1c1b233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407729824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2407729824
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2997591207
Short name T437
Test name
Test status
Simulation time 72263830 ps
CPU time 1.13 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 196256 kb
Host smart-901701a4-f0d5-4485-b4d9-2bfce7d18b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997591207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2997591207
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2380201586
Short name T468
Test name
Test status
Simulation time 50141772 ps
CPU time 2.02 seconds
Started Aug 16 05:11:51 PM PDT 24
Finished Aug 16 05:11:54 PM PDT 24
Peak memory 198156 kb
Host smart-8b05cf9d-5bbf-46e4-9ade-c2554a8e710b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380201586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2380201586
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1960277281
Short name T159
Test name
Test status
Simulation time 96200377 ps
CPU time 2.89 seconds
Started Aug 16 05:12:05 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 197300 kb
Host smart-e9d95859-073c-485b-b0f2-765dc29342dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960277281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1960277281
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3727865780
Short name T411
Test name
Test status
Simulation time 27720052 ps
CPU time 0.82 seconds
Started Aug 16 05:11:48 PM PDT 24
Finished Aug 16 05:11:49 PM PDT 24
Peak memory 196756 kb
Host smart-1b94c040-5059-4c94-aecf-38f85ec1ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727865780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3727865780
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3549837446
Short name T507
Test name
Test status
Simulation time 65145202 ps
CPU time 1.24 seconds
Started Aug 16 05:11:42 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 197212 kb
Host smart-e9e64b16-00df-491b-a86b-3e0e08edea9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549837446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3549837446
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.26813877
Short name T499
Test name
Test status
Simulation time 968811153 ps
CPU time 4.17 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 198144 kb
Host smart-dc368c15-94fb-41a2-89d9-73c583e03a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26813877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand
om_long_reg_writes_reg_reads.26813877
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.656895411
Short name T362
Test name
Test status
Simulation time 34893518 ps
CPU time 0.84 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 196376 kb
Host smart-1874df14-ed3f-4f03-b671-56e73c2b355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656895411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.656895411
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1428963614
Short name T204
Test name
Test status
Simulation time 42232673 ps
CPU time 0.92 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:40 PM PDT 24
Peak memory 195880 kb
Host smart-9b1fe7d1-8c57-41c8-9175-0389d8abe81d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428963614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1428963614
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3954742282
Short name T135
Test name
Test status
Simulation time 5515310763 ps
CPU time 34.43 seconds
Started Aug 16 05:11:53 PM PDT 24
Finished Aug 16 05:12:27 PM PDT 24
Peak memory 198264 kb
Host smart-1ac12162-03e3-44b0-83a2-76021622c0c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954742282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3954742282
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2249095859
Short name T14
Test name
Test status
Simulation time 14323589 ps
CPU time 0.58 seconds
Started Aug 16 05:12:01 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 194920 kb
Host smart-6fa2d839-9952-444d-ae77-0fc99ee20ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249095859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2249095859
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.668084368
Short name T148
Test name
Test status
Simulation time 32138476 ps
CPU time 0.83 seconds
Started Aug 16 05:12:01 PM PDT 24
Finished Aug 16 05:12:02 PM PDT 24
Peak memory 196700 kb
Host smart-4af4325d-9506-45fd-8a72-6c7489ba2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668084368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.668084368
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3202079922
Short name T212
Test name
Test status
Simulation time 1160730593 ps
CPU time 17.53 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:57 PM PDT 24
Peak memory 198220 kb
Host smart-666de51a-f57e-410c-a008-20cfd710043b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202079922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3202079922
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.799969348
Short name T184
Test name
Test status
Simulation time 92658599 ps
CPU time 1.05 seconds
Started Aug 16 05:11:42 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 196620 kb
Host smart-6950bfb1-db27-4bc4-ad94-076293cfe75f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799969348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.799969348
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3590171979
Short name T127
Test name
Test status
Simulation time 314716476 ps
CPU time 0.98 seconds
Started Aug 16 05:11:51 PM PDT 24
Finished Aug 16 05:11:52 PM PDT 24
Peak memory 196272 kb
Host smart-cbb52c63-02f7-4b2e-b239-75754f8abb1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590171979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3590171979
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3867651848
Short name T694
Test name
Test status
Simulation time 147598294 ps
CPU time 1.04 seconds
Started Aug 16 05:11:57 PM PDT 24
Finished Aug 16 05:11:58 PM PDT 24
Peak memory 196236 kb
Host smart-1eb612b4-0553-4e90-a1d7-36fbbcf7a0ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867651848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3867651848
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3065418518
Short name T675
Test name
Test status
Simulation time 134428486 ps
CPU time 3.15 seconds
Started Aug 16 05:11:42 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 198196 kb
Host smart-010106e5-2bfa-4d64-adbb-8d0579041c0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065418518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3065418518
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.224502266
Short name T445
Test name
Test status
Simulation time 502123326 ps
CPU time 0.98 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 196164 kb
Host smart-3798ac76-f389-4855-ac38-81b3546780cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224502266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.224502266
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1244829524
Short name T529
Test name
Test status
Simulation time 66176083 ps
CPU time 0.84 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 197364 kb
Host smart-8850ef15-f819-4c5f-9a15-a8344c2e9736
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244829524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1244829524
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3889962052
Short name T339
Test name
Test status
Simulation time 157473490 ps
CPU time 2.13 seconds
Started Aug 16 05:11:36 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 198128 kb
Host smart-a7bc9b7c-b2c3-4448-aa75-98c7061aea8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889962052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3889962052
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2351029313
Short name T634
Test name
Test status
Simulation time 178951082 ps
CPU time 1.35 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 195612 kb
Host smart-d571da06-da94-49da-8e5d-e953f7b75d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351029313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2351029313
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4092773266
Short name T214
Test name
Test status
Simulation time 589654144 ps
CPU time 1.11 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 195632 kb
Host smart-1f8b25d4-df28-45dc-8325-d93b304afef1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092773266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4092773266
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1675558948
Short name T6
Test name
Test status
Simulation time 11609707481 ps
CPU time 100.04 seconds
Started Aug 16 05:11:33 PM PDT 24
Finished Aug 16 05:13:13 PM PDT 24
Peak memory 198328 kb
Host smart-a2cae708-c689-4518-ba14-0e449d1621df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675558948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1675558948
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2363864404
Short name T57
Test name
Test status
Simulation time 31269670945 ps
CPU time 148.39 seconds
Started Aug 16 05:11:42 PM PDT 24
Finished Aug 16 05:14:10 PM PDT 24
Peak memory 198604 kb
Host smart-ead1ce15-f891-4cac-8c26-93f2306841d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2363864404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2363864404
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1439140424
Short name T196
Test name
Test status
Simulation time 125515095 ps
CPU time 0.57 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 193996 kb
Host smart-606de30b-cb01-49d4-9c92-94a8ea273bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439140424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1439140424
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.47911292
Short name T136
Test name
Test status
Simulation time 83764002 ps
CPU time 0.97 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:39 PM PDT 24
Peak memory 196096 kb
Host smart-31e11317-aa0b-4fa3-822b-705222d4c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47911292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.47911292
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1450594998
Short name T271
Test name
Test status
Simulation time 435409279 ps
CPU time 22.12 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:12:00 PM PDT 24
Peak memory 197096 kb
Host smart-08f59b6a-f1aa-4f2d-b3a8-3b7e2d196aff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450594998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1450594998
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1021064412
Short name T576
Test name
Test status
Simulation time 125519958 ps
CPU time 0.71 seconds
Started Aug 16 05:11:37 PM PDT 24
Finished Aug 16 05:11:38 PM PDT 24
Peak memory 195560 kb
Host smart-06f4fa0b-919a-4c4b-8040-52b51e6e0dd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021064412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1021064412
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.646156651
Short name T703
Test name
Test status
Simulation time 139206252 ps
CPU time 1.03 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 195948 kb
Host smart-0f27a002-ccae-4ffb-a099-b3cb13739018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646156651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.646156651
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.423869806
Short name T369
Test name
Test status
Simulation time 200525603 ps
CPU time 1.61 seconds
Started Aug 16 05:11:43 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 196668 kb
Host smart-2465ca28-28c3-497e-a795-16e046130259
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423869806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.423869806
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3490443491
Short name T256
Test name
Test status
Simulation time 717235218 ps
CPU time 3.11 seconds
Started Aug 16 05:11:56 PM PDT 24
Finished Aug 16 05:11:59 PM PDT 24
Peak memory 197232 kb
Host smart-5af5caf8-db04-4db9-9503-73cbbaf9e138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490443491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3490443491
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.637885906
Short name T597
Test name
Test status
Simulation time 57816714 ps
CPU time 1.22 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:43 PM PDT 24
Peak memory 198264 kb
Host smart-a09640ad-4be2-486e-adee-a05bfbe2b4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637885906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.637885906
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2814532308
Short name T700
Test name
Test status
Simulation time 30796603 ps
CPU time 1.08 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:41 PM PDT 24
Peak memory 196152 kb
Host smart-cd3d0cc4-2c72-4a09-8841-3154e22421a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814532308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2814532308
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1830047138
Short name T24
Test name
Test status
Simulation time 401719855 ps
CPU time 4.65 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 198132 kb
Host smart-483f19a4-0b34-4e0f-8fe0-d06d274c7363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830047138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1830047138
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2439368469
Short name T126
Test name
Test status
Simulation time 50663721 ps
CPU time 0.82 seconds
Started Aug 16 05:12:07 PM PDT 24
Finished Aug 16 05:12:08 PM PDT 24
Peak memory 195460 kb
Host smart-6c3c782a-a0f0-4db6-91eb-d4fa8c96ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439368469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2439368469
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2983712085
Short name T152
Test name
Test status
Simulation time 105787104 ps
CPU time 0.94 seconds
Started Aug 16 05:12:03 PM PDT 24
Finished Aug 16 05:12:04 PM PDT 24
Peak memory 196520 kb
Host smart-263e9a58-cecb-4180-a2bd-1513117b44c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983712085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2983712085
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2230722209
Short name T514
Test name
Test status
Simulation time 36230187712 ps
CPU time 99.64 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:13:24 PM PDT 24
Peak memory 198272 kb
Host smart-9c747a72-1d89-4620-bbd3-cae1eb731ccb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230722209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2230722209
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2484349694
Short name T28
Test name
Test status
Simulation time 2130678990 ps
CPU time 76.68 seconds
Started Aug 16 05:11:38 PM PDT 24
Finished Aug 16 05:12:55 PM PDT 24
Peak memory 198308 kb
Host smart-67e8dece-265e-4995-85eb-070c79871370
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2484349694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2484349694
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3431361638
Short name T519
Test name
Test status
Simulation time 46346664 ps
CPU time 0.54 seconds
Started Aug 16 05:11:47 PM PDT 24
Finished Aug 16 05:11:47 PM PDT 24
Peak memory 194044 kb
Host smart-941c7f79-8636-4fd0-bf76-5068e0a5549e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431361638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3431361638
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.361449619
Short name T185
Test name
Test status
Simulation time 160154001 ps
CPU time 0.94 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:36 PM PDT 24
Peak memory 197264 kb
Host smart-6810759c-9c94-4dcb-acac-c26389cef98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361449619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.361449619
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1834475211
Short name T481
Test name
Test status
Simulation time 1534863952 ps
CPU time 9.26 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:49 PM PDT 24
Peak memory 197028 kb
Host smart-df07c00e-c860-4843-b88f-375f0c7b8f44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834475211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1834475211
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.633835336
Short name T586
Test name
Test status
Simulation time 80516521 ps
CPU time 0.97 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 197084 kb
Host smart-4f438907-c68e-4bb4-99df-5d8bb45cbce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633835336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.633835336
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.23522226
Short name T364
Test name
Test status
Simulation time 26582041 ps
CPU time 0.74 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 195504 kb
Host smart-b6e83623-6912-4cea-9ded-65148eef1523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23522226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.23522226
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1542900014
Short name T625
Test name
Test status
Simulation time 68038012 ps
CPU time 2.66 seconds
Started Aug 16 05:11:47 PM PDT 24
Finished Aug 16 05:11:50 PM PDT 24
Peak memory 198220 kb
Host smart-97a684cf-10e5-4b2e-8874-63476083cdef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542900014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1542900014
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.949722732
Short name T670
Test name
Test status
Simulation time 57478358 ps
CPU time 1.76 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 196996 kb
Host smart-62354f59-5b96-4f8b-95ef-e67c27e88df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949722732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
949722732
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3026469096
Short name T273
Test name
Test status
Simulation time 41118809 ps
CPU time 0.84 seconds
Started Aug 16 05:11:52 PM PDT 24
Finished Aug 16 05:11:53 PM PDT 24
Peak memory 197408 kb
Host smart-14e07137-c2af-469d-a994-3d5697952d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026469096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3026469096
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1632801417
Short name T407
Test name
Test status
Simulation time 67718209 ps
CPU time 1.15 seconds
Started Aug 16 05:11:35 PM PDT 24
Finished Aug 16 05:11:37 PM PDT 24
Peak memory 198120 kb
Host smart-e5ffe772-1297-4655-bd85-fc71622bff0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632801417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1632801417
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.112030285
Short name T701
Test name
Test status
Simulation time 760045158 ps
CPU time 6.21 seconds
Started Aug 16 05:12:06 PM PDT 24
Finished Aug 16 05:12:13 PM PDT 24
Peak memory 198116 kb
Host smart-66a29312-2405-4c60-b3a1-7da2a9dfeb25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112030285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.112030285
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4276306678
Short name T290
Test name
Test status
Simulation time 175449122 ps
CPU time 0.99 seconds
Started Aug 16 05:11:41 PM PDT 24
Finished Aug 16 05:11:42 PM PDT 24
Peak memory 195836 kb
Host smart-ec005212-7f33-4017-b22f-f76f60ba4f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276306678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4276306678
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3497537358
Short name T476
Test name
Test status
Simulation time 32596672 ps
CPU time 1.09 seconds
Started Aug 16 05:11:44 PM PDT 24
Finished Aug 16 05:11:45 PM PDT 24
Peak memory 195680 kb
Host smart-afe6df3e-33c7-4928-bb15-20ea61ca567d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497537358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3497537358
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2925856063
Short name T521
Test name
Test status
Simulation time 17908267497 ps
CPU time 200.35 seconds
Started Aug 16 05:11:40 PM PDT 24
Finished Aug 16 05:15:01 PM PDT 24
Peak memory 198368 kb
Host smart-165dcbb4-b5c5-436a-b0a5-826d5ceaeeb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925856063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2925856063
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3969899813
Short name T56
Test name
Test status
Simulation time 12105347325 ps
CPU time 53.54 seconds
Started Aug 16 05:11:39 PM PDT 24
Finished Aug 16 05:12:33 PM PDT 24
Peak memory 198536 kb
Host smart-042bbdaf-869a-4f4d-8868-b17e6f786442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3969899813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3969899813
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2196724413
Short name T584
Test name
Test status
Simulation time 38718142 ps
CPU time 0.58 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:27 PM PDT 24
Peak memory 195796 kb
Host smart-0e54b379-23e4-4e27-a6be-20d906031768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196724413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2196724413
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2070281585
Short name T416
Test name
Test status
Simulation time 122963781 ps
CPU time 0.78 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:25 PM PDT 24
Peak memory 195348 kb
Host smart-11325937-cfa1-4d2d-9191-d78d041f8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070281585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2070281585
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.491833709
Short name T589
Test name
Test status
Simulation time 567284574 ps
CPU time 4.68 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:31 PM PDT 24
Peak memory 195660 kb
Host smart-637da7e9-1772-4847-b5a7-9cd3d42d7348
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491833709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.491833709
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3365143907
Short name T177
Test name
Test status
Simulation time 73307945 ps
CPU time 0.66 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 194472 kb
Host smart-caf9c7c1-35d5-47e8-b56c-78405e840c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365143907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3365143907
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.468932512
Short name T370
Test name
Test status
Simulation time 52967946 ps
CPU time 0.71 seconds
Started Aug 16 05:10:41 PM PDT 24
Finished Aug 16 05:10:42 PM PDT 24
Peak memory 194480 kb
Host smart-4c1d9579-e2bb-4aa2-8565-880f00ec0e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468932512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.468932512
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3747181485
Short name T585
Test name
Test status
Simulation time 60203219 ps
CPU time 1.38 seconds
Started Aug 16 05:10:30 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 196648 kb
Host smart-fd04efcf-5982-45ae-b362-ee746e015012
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747181485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3747181485
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2405295927
Short name T147
Test name
Test status
Simulation time 100370942 ps
CPU time 2.07 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:28 PM PDT 24
Peak memory 196828 kb
Host smart-74869c7d-8ab6-4a77-8028-d13c8e35e18d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405295927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2405295927
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3501105986
Short name T436
Test name
Test status
Simulation time 190640284 ps
CPU time 1.11 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 196084 kb
Host smart-3676582d-25ae-4753-aafb-a53fbd7d7ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501105986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3501105986
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3314784551
Short name T467
Test name
Test status
Simulation time 21478335 ps
CPU time 0.88 seconds
Started Aug 16 05:10:25 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 197456 kb
Host smart-39913adc-cb1a-458b-9151-199b4dd41f93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314784551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3314784551
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2701276179
Short name T230
Test name
Test status
Simulation time 94203191 ps
CPU time 4.56 seconds
Started Aug 16 05:10:21 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 198112 kb
Host smart-533a3d46-1ea8-456c-844e-2c1fd1cdbcf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701276179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2701276179
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3300557696
Short name T49
Test name
Test status
Simulation time 28075102 ps
CPU time 0.86 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 195488 kb
Host smart-d324bc4f-ab31-420e-b140-23f0948a273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300557696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3300557696
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3897572658
Short name T557
Test name
Test status
Simulation time 45154750 ps
CPU time 0.84 seconds
Started Aug 16 05:10:29 PM PDT 24
Finished Aug 16 05:10:30 PM PDT 24
Peak memory 195296 kb
Host smart-710cbd46-d9f0-4467-a85b-104dde194033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897572658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3897572658
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1972003458
Short name T699
Test name
Test status
Simulation time 13046932578 ps
CPU time 162.44 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:13:09 PM PDT 24
Peak memory 198312 kb
Host smart-9acc9705-9172-4077-9c8e-e3ff030b0ef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972003458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1972003458
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2831785674
Short name T232
Test name
Test status
Simulation time 26832035 ps
CPU time 0.56 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:10:37 PM PDT 24
Peak memory 192860 kb
Host smart-4c080a20-dba2-47bb-9a41-09376c1ee12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831785674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2831785674
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1302036673
Short name T237
Test name
Test status
Simulation time 61636270 ps
CPU time 0.76 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 195304 kb
Host smart-21e40ed0-4e70-40e3-89aa-207b32eb24a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302036673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1302036673
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.628726460
Short name T485
Test name
Test status
Simulation time 470499916 ps
CPU time 6.27 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:42 PM PDT 24
Peak memory 196972 kb
Host smart-f882a6f3-9efa-4757-8dfd-3dbbacf276fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628726460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.628726460
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3025501954
Short name T473
Test name
Test status
Simulation time 294986974 ps
CPU time 1 seconds
Started Aug 16 05:10:29 PM PDT 24
Finished Aug 16 05:10:30 PM PDT 24
Peak memory 197256 kb
Host smart-c4f5129b-cff5-440c-a64a-0879ccd30c6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025501954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3025501954
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3901141956
Short name T604
Test name
Test status
Simulation time 130420976 ps
CPU time 0.84 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 195480 kb
Host smart-c5e89b25-8987-459a-879b-2490e16d062c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901141956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3901141956
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1537416343
Short name T562
Test name
Test status
Simulation time 404431447 ps
CPU time 2.73 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:31 PM PDT 24
Peak memory 198220 kb
Host smart-04a2c0bb-26b8-4819-8eb7-4d1b584a7352
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537416343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1537416343
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.769386384
Short name T656
Test name
Test status
Simulation time 89320883 ps
CPU time 0.91 seconds
Started Aug 16 05:10:30 PM PDT 24
Finished Aug 16 05:10:31 PM PDT 24
Peak memory 195520 kb
Host smart-48319f71-a3fc-4948-9216-9a6f632ebaca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769386384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.769386384
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3271942016
Short name T390
Test name
Test status
Simulation time 219112399 ps
CPU time 1.36 seconds
Started Aug 16 05:10:16 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 197188 kb
Host smart-51734da7-6e67-4c11-b757-d00cddcadc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271942016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3271942016
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2747384815
Short name T245
Test name
Test status
Simulation time 36796295 ps
CPU time 0.83 seconds
Started Aug 16 05:10:26 PM PDT 24
Finished Aug 16 05:10:27 PM PDT 24
Peak memory 196688 kb
Host smart-ceda4468-784d-4403-9272-e18b698be21b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747384815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2747384815
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2008969468
Short name T642
Test name
Test status
Simulation time 458157984 ps
CPU time 2.76 seconds
Started Aug 16 05:10:29 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 198192 kb
Host smart-7438cbc5-3849-4888-85be-78751ae95712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008969468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2008969468
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1644095203
Short name T94
Test name
Test status
Simulation time 43237044 ps
CPU time 0.82 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 195424 kb
Host smart-f074393c-ad13-49ec-881e-c66191e04aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644095203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1644095203
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3333360237
Short name T412
Test name
Test status
Simulation time 127890848 ps
CPU time 1.17 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 195700 kb
Host smart-173e67d4-7ea9-458c-94ce-b5582d45fa66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333360237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3333360237
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2386732784
Short name T662
Test name
Test status
Simulation time 26064487903 ps
CPU time 172.77 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:13:27 PM PDT 24
Peak memory 198284 kb
Host smart-5eba7214-8429-439e-a41e-cb34b25032cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386732784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2386732784
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2292881278
Short name T59
Test name
Test status
Simulation time 6114587099 ps
CPU time 216.53 seconds
Started Aug 16 05:10:30 PM PDT 24
Finished Aug 16 05:14:07 PM PDT 24
Peak memory 198516 kb
Host smart-a7ae64d2-810c-4d6a-91b4-0104b56f8d58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2292881278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2292881278
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.449583088
Short name T392
Test name
Test status
Simulation time 18689042 ps
CPU time 0.59 seconds
Started Aug 16 05:10:21 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 194024 kb
Host smart-b294ffe7-dba1-4242-b5e9-71b9757b8596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449583088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.449583088
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2077647661
Short name T303
Test name
Test status
Simulation time 473581346 ps
CPU time 0.97 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 196724 kb
Host smart-8e4d6a21-46fb-404d-b9d5-8ccfb8f8e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077647661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2077647661
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1861975130
Short name T267
Test name
Test status
Simulation time 404508833 ps
CPU time 21.33 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:53 PM PDT 24
Peak memory 197088 kb
Host smart-0f2be8d0-87ec-4c71-9291-25276739b387
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861975130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1861975130
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1515039590
Short name T502
Test name
Test status
Simulation time 60425782 ps
CPU time 0.9 seconds
Started Aug 16 05:10:19 PM PDT 24
Finished Aug 16 05:10:20 PM PDT 24
Peak memory 196684 kb
Host smart-c2017346-4982-4ce5-a073-556d44c5a7f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515039590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1515039590
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.170793858
Short name T263
Test name
Test status
Simulation time 82587962 ps
CPU time 1.18 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 196000 kb
Host smart-4b9a83cc-f851-4903-9653-34ba6e91848f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170793858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.170793858
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1848055457
Short name T463
Test name
Test status
Simulation time 248578194 ps
CPU time 2.44 seconds
Started Aug 16 05:10:16 PM PDT 24
Finished Aug 16 05:10:19 PM PDT 24
Peak memory 198176 kb
Host smart-9652ab22-574c-4d77-ad3f-17e2be53b38d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848055457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1848055457
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3840305113
Short name T312
Test name
Test status
Simulation time 200535026 ps
CPU time 2.99 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 198224 kb
Host smart-fb631bf8-615b-4897-9bc6-a9e6d37bcbaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840305113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3840305113
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1756773560
Short name T298
Test name
Test status
Simulation time 19233768 ps
CPU time 0.81 seconds
Started Aug 16 05:10:23 PM PDT 24
Finished Aug 16 05:10:24 PM PDT 24
Peak memory 196060 kb
Host smart-32d21f44-ef93-4b26-a696-6318ab5ccaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756773560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1756773560
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4288281151
Short name T270
Test name
Test status
Simulation time 40614523 ps
CPU time 0.93 seconds
Started Aug 16 05:10:27 PM PDT 24
Finished Aug 16 05:10:28 PM PDT 24
Peak memory 196176 kb
Host smart-3bcf2c4d-ba59-42f3-bee4-dcaa02c66a9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288281151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4288281151
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3333732215
Short name T682
Test name
Test status
Simulation time 176897909 ps
CPU time 4.22 seconds
Started Aug 16 05:10:22 PM PDT 24
Finished Aug 16 05:10:27 PM PDT 24
Peak memory 198184 kb
Host smart-7ae80d00-a95e-465f-acc6-e66cd4c00b21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333732215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3333732215
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2702449718
Short name T672
Test name
Test status
Simulation time 615258529 ps
CPU time 1.25 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 195944 kb
Host smart-958500d2-644f-4d0a-b50d-ec478b3646a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702449718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2702449718
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3469121463
Short name T110
Test name
Test status
Simulation time 220972590 ps
CPU time 1.37 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 196940 kb
Host smart-8e510451-94ef-4ecc-aebd-0a1bc5cb61d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469121463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3469121463
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1184804955
Short name T354
Test name
Test status
Simulation time 17502402464 ps
CPU time 94.5 seconds
Started Aug 16 05:10:40 PM PDT 24
Finished Aug 16 05:12:15 PM PDT 24
Peak memory 198340 kb
Host smart-1a3a067c-14ce-4aba-b1dc-6cc0aaa79188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184804955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1184804955
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.97541343
Short name T553
Test name
Test status
Simulation time 14870766141 ps
CPU time 140.95 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:12:52 PM PDT 24
Peak memory 198568 kb
Host smart-7a9b2313-7940-4a12-bba8-13efe03b81eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=97541343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.97541343
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1462226674
Short name T116
Test name
Test status
Simulation time 26466468 ps
CPU time 0.56 seconds
Started Aug 16 05:10:25 PM PDT 24
Finished Aug 16 05:10:26 PM PDT 24
Peak memory 194240 kb
Host smart-17757c33-cd2b-410b-a1e3-4e8cab3f1e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462226674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1462226674
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1665556008
Short name T63
Test name
Test status
Simulation time 154308068 ps
CPU time 0.75 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:32 PM PDT 24
Peak memory 194920 kb
Host smart-de9ae07f-0d7a-4863-b53e-1e493974d2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665556008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1665556008
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2701729187
Short name T603
Test name
Test status
Simulation time 963923828 ps
CPU time 11.48 seconds
Started Aug 16 05:10:31 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 198188 kb
Host smart-99b088f5-025f-4b96-8ec0-8d1027b9ea33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701729187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2701729187
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3281152507
Short name T317
Test name
Test status
Simulation time 22251031 ps
CPU time 0.62 seconds
Started Aug 16 05:10:27 PM PDT 24
Finished Aug 16 05:10:28 PM PDT 24
Peak memory 194344 kb
Host smart-e1978911-d929-4a69-9bd7-d6dbf3c7ab56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281152507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3281152507
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1687235091
Short name T319
Test name
Test status
Simulation time 30372529 ps
CPU time 0.93 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 196172 kb
Host smart-bea6d99a-cb4d-495a-adf3-dc9ede56c109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687235091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1687235091
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2072942987
Short name T593
Test name
Test status
Simulation time 59127679 ps
CPU time 2.14 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 198180 kb
Host smart-492d5df8-1b82-417d-b6c9-c31d90675100
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072942987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2072942987
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.213536072
Short name T186
Test name
Test status
Simulation time 104153502 ps
CPU time 1.03 seconds
Started Aug 16 05:10:17 PM PDT 24
Finished Aug 16 05:10:18 PM PDT 24
Peak memory 195844 kb
Host smart-6fd09d94-a94e-4b7e-a619-4074c8777d21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213536072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.213536072
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2895876486
Short name T503
Test name
Test status
Simulation time 87481420 ps
CPU time 0.78 seconds
Started Aug 16 05:10:21 PM PDT 24
Finished Aug 16 05:10:22 PM PDT 24
Peak memory 195644 kb
Host smart-36b65cef-6f65-4e21-8ea1-7f2f6f29d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895876486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2895876486
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2308343941
Short name T624
Test name
Test status
Simulation time 30783236 ps
CPU time 1.13 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:39 PM PDT 24
Peak memory 198200 kb
Host smart-9c898f28-5505-4354-895b-4350917ea2b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308343941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2308343941
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1680103693
Short name T525
Test name
Test status
Simulation time 1650207914 ps
CPU time 4.73 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 198140 kb
Host smart-65c1b1fb-d799-44bd-9e91-481cc38e9d70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680103693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1680103693
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2220464177
Short name T294
Test name
Test status
Simulation time 34274807 ps
CPU time 0.93 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:29 PM PDT 24
Peak memory 195588 kb
Host smart-51f72720-ac3f-44d7-b0b9-05e2900229c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220464177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2220464177
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2729890016
Short name T95
Test name
Test status
Simulation time 70908571 ps
CPU time 1.06 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:39 PM PDT 24
Peak memory 195656 kb
Host smart-c25a9fc3-bef0-4470-9234-97c5ece0f06b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729890016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2729890016
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2588853005
Short name T247
Test name
Test status
Simulation time 19216471164 ps
CPU time 120.74 seconds
Started Aug 16 05:10:36 PM PDT 24
Finished Aug 16 05:12:38 PM PDT 24
Peak memory 198296 kb
Host smart-b9bd12d1-e881-403f-ad70-ccb7110eb5c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588853005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2588853005
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3071700622
Short name T58
Test name
Test status
Simulation time 1928584115 ps
CPU time 68.97 seconds
Started Aug 16 05:10:24 PM PDT 24
Finished Aug 16 05:11:33 PM PDT 24
Peak memory 198344 kb
Host smart-37701c45-fe0e-4e55-ab2b-20fd61dc44b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3071700622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3071700622
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2270377202
Short name T261
Test name
Test status
Simulation time 10999411 ps
CPU time 0.58 seconds
Started Aug 16 05:10:34 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 194096 kb
Host smart-a117c66c-03bf-437c-b760-7812333c3cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270377202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2270377202
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3897100560
Short name T654
Test name
Test status
Simulation time 71278513 ps
CPU time 0.67 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 195012 kb
Host smart-c9b2e9c0-637c-4f0e-ac81-57fcd278abb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897100560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3897100560
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3478317538
Short name T605
Test name
Test status
Simulation time 4694714492 ps
CPU time 26.39 seconds
Started Aug 16 05:10:38 PM PDT 24
Finished Aug 16 05:11:04 PM PDT 24
Peak memory 198296 kb
Host smart-ee0fcb53-d116-4709-852c-90bd7a606921
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478317538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3478317538
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2651159360
Short name T494
Test name
Test status
Simulation time 334652897 ps
CPU time 0.88 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:34 PM PDT 24
Peak memory 196676 kb
Host smart-da6164b1-f177-4a36-8641-0835606165c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651159360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2651159360
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.755197847
Short name T11
Test name
Test status
Simulation time 54057918 ps
CPU time 1.32 seconds
Started Aug 16 05:10:33 PM PDT 24
Finished Aug 16 05:10:35 PM PDT 24
Peak memory 198216 kb
Host smart-6ae81280-2807-4b11-b8e5-0010d4315530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755197847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.755197847
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3103333344
Short name T483
Test name
Test status
Simulation time 67423141 ps
CPU time 2.64 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:40 PM PDT 24
Peak memory 198240 kb
Host smart-f0c13c73-fd71-429d-a50d-ff0e9db00ed1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103333344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3103333344
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1613081093
Short name T168
Test name
Test status
Simulation time 122316941 ps
CPU time 2.02 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:38 PM PDT 24
Peak memory 197136 kb
Host smart-3cda8e0b-1c30-4b33-bad1-1077dd654ce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613081093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1613081093
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.454626902
Short name T617
Test name
Test status
Simulation time 31017206 ps
CPU time 0.71 seconds
Started Aug 16 05:10:30 PM PDT 24
Finished Aug 16 05:10:30 PM PDT 24
Peak memory 195580 kb
Host smart-f6f8dd94-b34f-40f2-9370-26e5aba14ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454626902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.454626902
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1801828739
Short name T430
Test name
Test status
Simulation time 116338668 ps
CPU time 1.25 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:10:30 PM PDT 24
Peak memory 197188 kb
Host smart-2d30aba5-1a86-4543-8d21-a91f0e19ea72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801828739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1801828739
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1982005048
Short name T513
Test name
Test status
Simulation time 1187702916 ps
CPU time 5.17 seconds
Started Aug 16 05:10:37 PM PDT 24
Finished Aug 16 05:10:43 PM PDT 24
Peak memory 198128 kb
Host smart-a5025a8f-86cb-4c95-a8f2-2fef5280355c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982005048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1982005048
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.650947604
Short name T260
Test name
Test status
Simulation time 60973922 ps
CPU time 1.14 seconds
Started Aug 16 05:10:35 PM PDT 24
Finished Aug 16 05:10:36 PM PDT 24
Peak memory 196444 kb
Host smart-1318f795-48aa-4219-a181-0e5eded32f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650947604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.650947604
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3270347376
Short name T535
Test name
Test status
Simulation time 27365212 ps
CPU time 0.9 seconds
Started Aug 16 05:10:32 PM PDT 24
Finished Aug 16 05:10:33 PM PDT 24
Peak memory 197252 kb
Host smart-10fd734a-bc81-4b9d-b424-4e700ffd6577
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270347376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3270347376
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.542040037
Short name T563
Test name
Test status
Simulation time 18434376669 ps
CPU time 127.79 seconds
Started Aug 16 05:10:28 PM PDT 24
Finished Aug 16 05:12:36 PM PDT 24
Peak memory 198340 kb
Host smart-9a46fabb-8089-41e2-8646-afb25010c7d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542040037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.542040037
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.583583094
Short name T897
Test name
Test status
Simulation time 672755254 ps
CPU time 1.13 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 197176 kb
Host smart-ca767ce1-c077-499c-bf9b-e06a815da323
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=583583094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.583583094
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136629353
Short name T900
Test name
Test status
Simulation time 170510951 ps
CPU time 0.95 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 191112 kb
Host smart-1559a4f1-ddf1-4426-83f5-badb67fb6472
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136629353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.136629353
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1142247776
Short name T898
Test name
Test status
Simulation time 69967063 ps
CPU time 1.05 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 197644 kb
Host smart-9756bf4c-1a49-43d3-9173-576e9bb2358d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1142247776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1142247776
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.919354864
Short name T928
Test name
Test status
Simulation time 38814881 ps
CPU time 1.13 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 191352 kb
Host smart-1dc4a3b4-f8d3-41cc-af4f-1602ee178f20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919354864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.919354864
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1066078465
Short name T886
Test name
Test status
Simulation time 243556169 ps
CPU time 1.21 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191312 kb
Host smart-f136f032-8955-42e6-9026-4eaab0a18f29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1066078465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1066078465
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887133744
Short name T892
Test name
Test status
Simulation time 198160995 ps
CPU time 1.09 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191304 kb
Host smart-f89df732-38a4-4323-923a-252a9f1259bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887133744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2887133744
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1122038464
Short name T914
Test name
Test status
Simulation time 142592365 ps
CPU time 0.86 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191104 kb
Host smart-1850287e-d349-4aab-9f39-131ea9b21e03
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1122038464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1122038464
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2232515271
Short name T844
Test name
Test status
Simulation time 464116868 ps
CPU time 1.13 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 197128 kb
Host smart-d023d0ec-0891-42b2-b0bb-fadc579de932
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232515271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2232515271
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3031059742
Short name T921
Test name
Test status
Simulation time 114699258 ps
CPU time 0.84 seconds
Started Aug 16 05:01:28 PM PDT 24
Finished Aug 16 05:01:29 PM PDT 24
Peak memory 195812 kb
Host smart-85bc120f-3db6-4b0b-a7a4-126cef376a2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3031059742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3031059742
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3503144470
Short name T876
Test name
Test status
Simulation time 43457661 ps
CPU time 1.17 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191332 kb
Host smart-35b3c087-7ca0-43d0-aaca-57290b38f620
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503144470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3503144470
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3296433818
Short name T922
Test name
Test status
Simulation time 327068428 ps
CPU time 1.16 seconds
Started Aug 16 05:01:28 PM PDT 24
Finished Aug 16 05:01:29 PM PDT 24
Peak memory 191304 kb
Host smart-bc4b0e59-df94-43b3-9c0d-c22e5f297a4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3296433818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3296433818
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.703571805
Short name T901
Test name
Test status
Simulation time 73309609 ps
CPU time 1.22 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 197656 kb
Host smart-b594a7bc-639c-4481-aa81-407e3a7d29aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703571805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.703571805
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4244777393
Short name T894
Test name
Test status
Simulation time 167769072 ps
CPU time 0.88 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 195620 kb
Host smart-33c9d664-2661-4ae3-8361-37c2a8afd20c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4244777393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4244777393
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.873092423
Short name T863
Test name
Test status
Simulation time 50199297 ps
CPU time 1.35 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 191356 kb
Host smart-433251ed-ef6a-4ce5-888c-c16db981848c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873092423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.873092423
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1204035879
Short name T889
Test name
Test status
Simulation time 37839232 ps
CPU time 1.03 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191308 kb
Host smart-e748e38d-adb2-48c5-b2c7-5ab43b256390
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1204035879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1204035879
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4135172535
Short name T879
Test name
Test status
Simulation time 191777957 ps
CPU time 1.04 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191300 kb
Host smart-949bcae9-bccb-4a5a-85c9-7f4bbce97a27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135172535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4135172535
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1467896258
Short name T895
Test name
Test status
Simulation time 51683353 ps
CPU time 1.41 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 191348 kb
Host smart-f4215fdb-16ef-41b8-9c2c-48a2e718e749
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1467896258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1467896258
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3252350311
Short name T873
Test name
Test status
Simulation time 67765012 ps
CPU time 1.38 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191332 kb
Host smart-dc0fbacf-2d56-45ab-a1cf-f0dcfd54886e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252350311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3252350311
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2852750789
Short name T927
Test name
Test status
Simulation time 227778690 ps
CPU time 1 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191312 kb
Host smart-7305c797-546d-424a-91e3-07e9fb8b84c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2852750789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2852750789
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926061455
Short name T904
Test name
Test status
Simulation time 126609572 ps
CPU time 1.14 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 197672 kb
Host smart-5a005088-b251-47a3-af77-823ace303d55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926061455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.926061455
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2905491743
Short name T878
Test name
Test status
Simulation time 159334196 ps
CPU time 1.02 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191332 kb
Host smart-f6336b36-ce99-46f6-b533-c0ba706e8f19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2905491743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2905491743
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3001062173
Short name T935
Test name
Test status
Simulation time 105399976 ps
CPU time 0.89 seconds
Started Aug 16 05:01:34 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 197440 kb
Host smart-2032f717-aa16-4620-8525-2d9ab11b549a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001062173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3001062173
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2540769995
Short name T854
Test name
Test status
Simulation time 113411665 ps
CPU time 1.23 seconds
Started Aug 16 05:01:34 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 191312 kb
Host smart-30e0f9c6-0018-4150-8ca0-923e7bdca17b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2540769995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2540769995
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1957566813
Short name T923
Test name
Test status
Simulation time 46778101 ps
CPU time 0.81 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 191096 kb
Host smart-9c12bcd2-54f9-42f3-8970-78d4f0272aa6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957566813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1957566813
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1524074509
Short name T891
Test name
Test status
Simulation time 101857381 ps
CPU time 1.02 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 191248 kb
Host smart-e2d69868-ddca-4662-b55c-7072e7505bec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1524074509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1524074509
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1365495027
Short name T870
Test name
Test status
Simulation time 51826459 ps
CPU time 1.02 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 197032 kb
Host smart-75490650-68a9-40a5-86fe-8a598929be92
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365495027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1365495027
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3867514207
Short name T911
Test name
Test status
Simulation time 97886722 ps
CPU time 0.82 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 195784 kb
Host smart-9c194561-5e09-4f65-9788-952484d30244
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3867514207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3867514207
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.554319996
Short name T916
Test name
Test status
Simulation time 72481455 ps
CPU time 1.1 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 196044 kb
Host smart-04040abf-a2b9-4611-abb0-7c0b58bb3f5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554319996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.554319996
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.34634172
Short name T860
Test name
Test status
Simulation time 60812655 ps
CPU time 1.01 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 191296 kb
Host smart-d0c0f2e2-8eca-448a-80ba-590442479cc2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=34634172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.34634172
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3673411591
Short name T858
Test name
Test status
Simulation time 173199025 ps
CPU time 1.39 seconds
Started Aug 16 05:01:38 PM PDT 24
Finished Aug 16 05:01:40 PM PDT 24
Peak memory 197640 kb
Host smart-17777dfa-08a2-429a-8198-07593ac1050e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673411591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3673411591
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1244864780
Short name T931
Test name
Test status
Simulation time 564151532 ps
CPU time 1.12 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:37 PM PDT 24
Peak memory 191312 kb
Host smart-e92dcb41-aa9b-4ee3-ba0d-3bbbb570e70d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1244864780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1244864780
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2327704554
Short name T871
Test name
Test status
Simulation time 43062882 ps
CPU time 1.16 seconds
Started Aug 16 05:01:37 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 191240 kb
Host smart-4a840e8c-1f09-4071-bff3-cdb3660bb9a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327704554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2327704554
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4258656160
Short name T930
Test name
Test status
Simulation time 82433831 ps
CPU time 0.95 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:37 PM PDT 24
Peak memory 196948 kb
Host smart-846b4e12-2102-4022-a107-723a9f9f8ed8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4258656160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4258656160
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2064014110
Short name T880
Test name
Test status
Simulation time 161079552 ps
CPU time 0.84 seconds
Started Aug 16 05:01:40 PM PDT 24
Finished Aug 16 05:01:41 PM PDT 24
Peak memory 195624 kb
Host smart-5abdd3ce-6ee9-4e18-949a-0f5c19747fde
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064014110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2064014110
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2960031414
Short name T912
Test name
Test status
Simulation time 163473998 ps
CPU time 1.39 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 197576 kb
Host smart-ef45db26-cf8f-4887-89d6-b79ea4339aa0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2960031414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2960031414
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3389214780
Short name T925
Test name
Test status
Simulation time 78836941 ps
CPU time 1.27 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:37 PM PDT 24
Peak memory 197712 kb
Host smart-c2929997-839f-4038-b3fe-028d0428031d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389214780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3389214780
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3180896254
Short name T913
Test name
Test status
Simulation time 120511060 ps
CPU time 1.24 seconds
Started Aug 16 05:01:37 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 191292 kb
Host smart-c6853077-c478-4247-a1da-b64ce471007c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3180896254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3180896254
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.557219668
Short name T926
Test name
Test status
Simulation time 38906087 ps
CPU time 1.06 seconds
Started Aug 16 05:01:35 PM PDT 24
Finished Aug 16 05:01:36 PM PDT 24
Peak memory 191296 kb
Host smart-6aac08a4-71f1-445f-835e-1656c16647a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557219668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.557219668
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1978909909
Short name T866
Test name
Test status
Simulation time 49795665 ps
CPU time 0.96 seconds
Started Aug 16 05:01:34 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 196012 kb
Host smart-3511e3d9-e441-412f-ac3d-30cc3e39237c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1978909909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1978909909
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3490463624
Short name T920
Test name
Test status
Simulation time 30846087 ps
CPU time 0.81 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 191028 kb
Host smart-8fbf0616-367a-4928-90aa-6eba5518fd2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490463624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3490463624
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1951220526
Short name T837
Test name
Test status
Simulation time 166606978 ps
CPU time 1.21 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:01:52 PM PDT 24
Peak memory 191300 kb
Host smart-89cbdeee-450b-4382-acef-219104bbceae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1951220526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1951220526
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.30069385
Short name T868
Test name
Test status
Simulation time 490121361 ps
CPU time 0.97 seconds
Started Aug 16 05:01:38 PM PDT 24
Finished Aug 16 05:01:39 PM PDT 24
Peak memory 191316 kb
Host smart-e8a8bdf6-22c3-4809-9284-7dce2b82c952
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30069385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.30069385
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3369484697
Short name T910
Test name
Test status
Simulation time 84707977 ps
CPU time 1.23 seconds
Started Aug 16 05:01:38 PM PDT 24
Finished Aug 16 05:01:40 PM PDT 24
Peak memory 196032 kb
Host smart-26b91b88-297c-4945-bd99-5640c8ae8d06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3369484697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3369484697
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1620284605
Short name T907
Test name
Test status
Simulation time 283924820 ps
CPU time 1.23 seconds
Started Aug 16 05:01:36 PM PDT 24
Finished Aug 16 05:01:38 PM PDT 24
Peak memory 191296 kb
Host smart-930cd93a-da76-49eb-836f-fecb85800b75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620284605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1620284605
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4164192012
Short name T936
Test name
Test status
Simulation time 27814903 ps
CPU time 0.87 seconds
Started Aug 16 05:01:39 PM PDT 24
Finished Aug 16 05:01:40 PM PDT 24
Peak memory 195704 kb
Host smart-17d71bb5-32a6-49b6-9f90-a02b6e873541
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4164192012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4164192012
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2033150683
Short name T843
Test name
Test status
Simulation time 41013972 ps
CPU time 1.29 seconds
Started Aug 16 05:01:41 PM PDT 24
Finished Aug 16 05:01:43 PM PDT 24
Peak memory 197552 kb
Host smart-5b91db35-ad43-43bf-ac07-1a066b32ed2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033150683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2033150683
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3326469007
Short name T855
Test name
Test status
Simulation time 163432016 ps
CPU time 0.92 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:30 PM PDT 24
Peak memory 191092 kb
Host smart-d4eb7332-5187-4b9b-8522-2f7bd79df107
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3326469007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3326469007
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.609540265
Short name T851
Test name
Test status
Simulation time 141251297 ps
CPU time 1.36 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 197128 kb
Host smart-92d7a0fe-c4e6-4a5b-bdf6-2f02da9ef9f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609540265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.609540265
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4049217575
Short name T859
Test name
Test status
Simulation time 71338522 ps
CPU time 0.72 seconds
Started Aug 16 05:01:35 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 191108 kb
Host smart-6bca2b81-86f5-4f8d-8f31-313274af3926
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4049217575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4049217575
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3392335757
Short name T908
Test name
Test status
Simulation time 46660493 ps
CPU time 0.82 seconds
Started Aug 16 05:01:49 PM PDT 24
Finished Aug 16 05:01:50 PM PDT 24
Peak memory 191096 kb
Host smart-f5684c1a-c6b0-4439-92d6-6e8bcf6dba5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392335757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3392335757
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1227377427
Short name T882
Test name
Test status
Simulation time 70705406 ps
CPU time 1.29 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 191224 kb
Host smart-1a94f192-78b2-4f59-abfe-486ba49b5f7f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1227377427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1227377427
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2747111713
Short name T896
Test name
Test status
Simulation time 254562613 ps
CPU time 0.92 seconds
Started Aug 16 05:01:43 PM PDT 24
Finished Aug 16 05:01:44 PM PDT 24
Peak memory 191144 kb
Host smart-84f82a68-1ea8-415d-ad2c-2c65ec6b6cd4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747111713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2747111713
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1808161809
Short name T845
Test name
Test status
Simulation time 169932967 ps
CPU time 1.36 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191352 kb
Host smart-59c349fc-ebc3-4fe8-9504-937d7a0e78a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1808161809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1808161809
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2843493384
Short name T883
Test name
Test status
Simulation time 313026951 ps
CPU time 1.09 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191344 kb
Host smart-2e26795a-eb60-4641-859d-8d7b0061ac95
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843493384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2843493384
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.273213748
Short name T874
Test name
Test status
Simulation time 215774329 ps
CPU time 1.28 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 191216 kb
Host smart-23ddc266-fad7-4278-8851-cc33da445b04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=273213748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.273213748
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3139371489
Short name T890
Test name
Test status
Simulation time 70170201 ps
CPU time 1.16 seconds
Started Aug 16 05:01:48 PM PDT 24
Finished Aug 16 05:01:50 PM PDT 24
Peak memory 190980 kb
Host smart-9c73110a-a60f-4012-b252-cf1e67d6aab0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139371489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3139371489
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4214842845
Short name T893
Test name
Test status
Simulation time 136261413 ps
CPU time 1.1 seconds
Started Aug 16 05:01:46 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 197636 kb
Host smart-bdaffbd6-8f66-475e-9d01-c7674cf9256e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4214842845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4214842845
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2969982684
Short name T888
Test name
Test status
Simulation time 137615114 ps
CPU time 0.93 seconds
Started Aug 16 05:01:46 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 191080 kb
Host smart-71725a14-dd7a-4882-8c19-e5160d7eefc7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969982684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2969982684
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.556976310
Short name T856
Test name
Test status
Simulation time 80118502 ps
CPU time 1.5 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191340 kb
Host smart-fce1aa65-e0bb-4134-ad8f-2da546d1a109
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=556976310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.556976310
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1484621197
Short name T864
Test name
Test status
Simulation time 21213267 ps
CPU time 0.73 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 191112 kb
Host smart-167bfb88-1b66-4bfe-b4bf-ec59c9bee13a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484621197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1484621197
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2250498440
Short name T841
Test name
Test status
Simulation time 136235594 ps
CPU time 0.93 seconds
Started Aug 16 05:01:46 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 191108 kb
Host smart-d7547e71-4eb6-4a41-9000-fb870bf3e637
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2250498440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2250498440
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4178373525
Short name T875
Test name
Test status
Simulation time 94278548 ps
CPU time 0.95 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191312 kb
Host smart-f67a779f-a71f-42f3-a759-7b4fd95915a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178373525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4178373525
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3425264397
Short name T924
Test name
Test status
Simulation time 50347768 ps
CPU time 1.1 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 197624 kb
Host smart-178b9a1e-3487-4942-ac5f-88a534557210
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3425264397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3425264397
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.98034869
Short name T849
Test name
Test status
Simulation time 593671988 ps
CPU time 1.13 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 191312 kb
Host smart-c429f12b-4899-4721-844d-e33925f1d6db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98034869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.98034869
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2792417699
Short name T850
Test name
Test status
Simulation time 42494111 ps
CPU time 1.18 seconds
Started Aug 16 05:01:43 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191292 kb
Host smart-e4bcb2c6-bf6b-4e6a-8451-1e32757daced
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2792417699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2792417699
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1602355098
Short name T839
Test name
Test status
Simulation time 71930922 ps
CPU time 1.41 seconds
Started Aug 16 05:01:47 PM PDT 24
Finished Aug 16 05:01:49 PM PDT 24
Peak memory 197692 kb
Host smart-59223ca5-355f-43fc-832a-bb65432e241b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602355098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1602355098
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.317020828
Short name T853
Test name
Test status
Simulation time 262614010 ps
CPU time 1.24 seconds
Started Aug 16 05:01:43 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191220 kb
Host smart-dab27603-2eb2-45b0-a790-c8f23303e34f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=317020828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.317020828
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4191622948
Short name T848
Test name
Test status
Simulation time 58179978 ps
CPU time 1.09 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191308 kb
Host smart-2cc21dbd-e469-473d-b990-b8df5c8f9b75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191622948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4191622948
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1048647647
Short name T902
Test name
Test status
Simulation time 41368585 ps
CPU time 0.9 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:32 PM PDT 24
Peak memory 191112 kb
Host smart-a6665a59-9b87-4263-a547-f29ca5a78af4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1048647647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1048647647
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11342284
Short name T842
Test name
Test status
Simulation time 185699591 ps
CPU time 0.95 seconds
Started Aug 16 05:01:29 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 191060 kb
Host smart-d078d52d-8dd7-44c1-9c70-b5f807318fcf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.11342284
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3501453714
Short name T933
Test name
Test status
Simulation time 117392232 ps
CPU time 1.04 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 197640 kb
Host smart-7d2d96f8-e327-4e3c-9c1b-a850cf30bfb9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3501453714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3501453714
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4129927860
Short name T872
Test name
Test status
Simulation time 66722611 ps
CPU time 1.17 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 191316 kb
Host smart-906261f2-f07e-4f8b-b0b3-8dd530e57005
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129927860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4129927860
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.385593215
Short name T865
Test name
Test status
Simulation time 130538948 ps
CPU time 0.95 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191292 kb
Host smart-082761af-91c7-4e15-b8c7-9623816057a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=385593215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.385593215
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4107981363
Short name T885
Test name
Test status
Simulation time 20841207 ps
CPU time 0.73 seconds
Started Aug 16 05:01:48 PM PDT 24
Finished Aug 16 05:01:49 PM PDT 24
Peak memory 190740 kb
Host smart-ad1433da-719d-4ff0-b0ef-036fae0937f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107981363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4107981363
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2274710250
Short name T905
Test name
Test status
Simulation time 24539369 ps
CPU time 0.79 seconds
Started Aug 16 05:01:46 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 191128 kb
Host smart-d6ce6300-f87a-45c8-99fe-2ef289a51223
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2274710250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2274710250
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.751372796
Short name T857
Test name
Test status
Simulation time 345522633 ps
CPU time 1.55 seconds
Started Aug 16 05:01:43 PM PDT 24
Finished Aug 16 05:01:44 PM PDT 24
Peak memory 191296 kb
Host smart-830dfc9c-a60a-4e63-bdf8-340a8fec22ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751372796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.751372796
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4018724149
Short name T862
Test name
Test status
Simulation time 298022373 ps
CPU time 1.32 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 196932 kb
Host smart-7832f9c2-2809-4130-90ea-44c1b3d9727b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4018724149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4018724149
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1447788973
Short name T906
Test name
Test status
Simulation time 195913014 ps
CPU time 1.04 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191316 kb
Host smart-6111bc13-9722-48fe-9228-64506637a6ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447788973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1447788973
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1474804146
Short name T847
Test name
Test status
Simulation time 328418025 ps
CPU time 1.15 seconds
Started Aug 16 05:01:43 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191296 kb
Host smart-f801c93e-1db8-4eca-b6af-f76571eb9ae7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1474804146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1474804146
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1332118231
Short name T881
Test name
Test status
Simulation time 42450218 ps
CPU time 0.88 seconds
Started Aug 16 05:01:43 PM PDT 24
Finished Aug 16 05:01:44 PM PDT 24
Peak memory 191116 kb
Host smart-66f59000-7168-4e5b-a1b5-8dbf2fb80303
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332118231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1332118231
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3159241200
Short name T887
Test name
Test status
Simulation time 79386219 ps
CPU time 1.34 seconds
Started Aug 16 05:01:49 PM PDT 24
Finished Aug 16 05:01:50 PM PDT 24
Peak memory 197692 kb
Host smart-cf44f7ad-1549-49e2-bbaa-563d64d72e55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3159241200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3159241200
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101840289
Short name T869
Test name
Test status
Simulation time 203815611 ps
CPU time 0.95 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:45 PM PDT 24
Peak memory 191104 kb
Host smart-661df369-bafd-402d-b45c-5a84a022a689
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101840289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1101840289
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2764560942
Short name T903
Test name
Test status
Simulation time 47445438 ps
CPU time 1.5 seconds
Started Aug 16 05:01:44 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 197676 kb
Host smart-5b796fb9-ad3b-4fa3-9f96-b15178b4a3d4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2764560942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2764560942
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2167109421
Short name T846
Test name
Test status
Simulation time 142782788 ps
CPU time 0.79 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 191104 kb
Host smart-887e1e50-7405-4025-a9b6-a29230fe094e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167109421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2167109421
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3968382654
Short name T899
Test name
Test status
Simulation time 675352360 ps
CPU time 1.56 seconds
Started Aug 16 05:01:46 PM PDT 24
Finished Aug 16 05:01:47 PM PDT 24
Peak memory 191344 kb
Host smart-6cd0dcef-58a7-4c9c-8c72-f5da8a331c3f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3968382654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3968382654
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211645391
Short name T919
Test name
Test status
Simulation time 141290019 ps
CPU time 0.89 seconds
Started Aug 16 05:01:45 PM PDT 24
Finished Aug 16 05:01:46 PM PDT 24
Peak memory 191120 kb
Host smart-6120106b-c490-4c94-9d98-0f200e1b8085
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211645391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2211645391
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2659575961
Short name T932
Test name
Test status
Simulation time 73559557 ps
CPU time 1.22 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:01:53 PM PDT 24
Peak memory 191324 kb
Host smart-08f45817-07a8-4c3c-8ffe-b22cecd5459e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2659575961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2659575961
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3144683443
Short name T918
Test name
Test status
Simulation time 60843132 ps
CPU time 1.19 seconds
Started Aug 16 05:01:51 PM PDT 24
Finished Aug 16 05:01:53 PM PDT 24
Peak memory 191332 kb
Host smart-1d69d067-7626-4ebe-8e11-e9be45f5e752
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144683443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3144683443
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1927000962
Short name T917
Test name
Test status
Simulation time 188567024 ps
CPU time 1.05 seconds
Started Aug 16 05:01:52 PM PDT 24
Finished Aug 16 05:01:53 PM PDT 24
Peak memory 191116 kb
Host smart-8e60ce8d-2d68-46e5-b496-a497b3928942
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1927000962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1927000962
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1317002358
Short name T852
Test name
Test status
Simulation time 88580996 ps
CPU time 0.94 seconds
Started Aug 16 05:01:57 PM PDT 24
Finished Aug 16 05:01:58 PM PDT 24
Peak memory 191272 kb
Host smart-b9c634c5-7985-44bb-b14d-3aa4dab72178
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317002358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1317002358
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.947645161
Short name T909
Test name
Test status
Simulation time 33448484 ps
CPU time 0.76 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191092 kb
Host smart-7b8daaa7-d67e-4e81-bb0c-fb7ca8cfdd08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=947645161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.947645161
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3726173933
Short name T877
Test name
Test status
Simulation time 23887742 ps
CPU time 0.78 seconds
Started Aug 16 05:01:34 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 191104 kb
Host smart-6d3a255b-0199-4623-8606-8a50cfe9c0b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726173933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3726173933
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3793952045
Short name T840
Test name
Test status
Simulation time 385372450 ps
CPU time 1.46 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 197628 kb
Host smart-e21f0157-c038-4560-9ff0-9acdc87e0d26
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3793952045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3793952045
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2519364408
Short name T929
Test name
Test status
Simulation time 241806536 ps
CPU time 1.12 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191372 kb
Host smart-65ce298a-014e-4a8d-a37e-d0ed6b56854e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519364408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2519364408
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2054986099
Short name T884
Test name
Test status
Simulation time 121639789 ps
CPU time 1.04 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191332 kb
Host smart-10ebde2a-1ab4-49d2-9c3a-28b7a780233a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2054986099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2054986099
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.385795784
Short name T867
Test name
Test status
Simulation time 204196680 ps
CPU time 1.11 seconds
Started Aug 16 05:01:33 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191340 kb
Host smart-7d5969e8-2e0a-463e-b0c8-65e0aab09ad2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385795784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.385795784
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2320149625
Short name T861
Test name
Test status
Simulation time 57146032 ps
CPU time 0.95 seconds
Started Aug 16 05:01:31 PM PDT 24
Finished Aug 16 05:01:33 PM PDT 24
Peak memory 191128 kb
Host smart-9283473e-acff-4e7a-8938-01cee23542bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2320149625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2320149625
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.585744362
Short name T838
Test name
Test status
Simulation time 35191695 ps
CPU time 1.23 seconds
Started Aug 16 05:01:34 PM PDT 24
Finished Aug 16 05:01:35 PM PDT 24
Peak memory 197288 kb
Host smart-d928030d-986b-42fb-a2b0-be26631c414a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585744362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.585744362
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1850901007
Short name T915
Test name
Test status
Simulation time 148869139 ps
CPU time 1.28 seconds
Started Aug 16 05:01:30 PM PDT 24
Finished Aug 16 05:01:31 PM PDT 24
Peak memory 191328 kb
Host smart-abb8cd4b-51a7-45f4-98f4-0e5b8c9484fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1850901007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1850901007
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3562330593
Short name T934
Test name
Test status
Simulation time 50800322 ps
CPU time 1.31 seconds
Started Aug 16 05:01:32 PM PDT 24
Finished Aug 16 05:01:34 PM PDT 24
Peak memory 191220 kb
Host smart-ac1b48e8-e4d1-4b45-91f2-8065ebd0fe11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562330593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3562330593
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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