Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1640323	1			T22	157		T23	1		T24	1
all_pins[1]	1640323	1			T22	157		T23	1		T24	1
all_pins[2]	1640323	1			T22	157		T23	1		T24	1
all_pins[3]	1640323	1			T22	157		T23	1		T24	1
all_pins[4]	1640323	1			T22	157		T23	1		T24	1
all_pins[5]	1640323	1			T22	157		T23	1		T24	1
all_pins[6]	1640323	1			T22	157		T23	1		T24	1
all_pins[7]	1640323	1			T22	157		T23	1		T24	1
all_pins[8]	1640323	1			T22	157		T23	1		T24	1
all_pins[9]	1640323	1			T22	157		T23	1		T24	1
all_pins[10]	1640323	1			T22	157		T23	1		T24	1
all_pins[11]	1640323	1			T22	157		T23	1		T24	1
all_pins[12]	1640323	1			T22	157		T23	1		T24	1
all_pins[13]	1640323	1			T22	157		T23	1		T24	1
all_pins[14]	1640323	1			T22	157		T23	1		T24	1
all_pins[15]	1640323	1			T22	157		T23	1		T24	1
all_pins[16]	1640323	1			T22	157		T23	1		T24	1
all_pins[17]	1640323	1			T22	157		T23	1		T24	1
all_pins[18]	1640323	1			T22	157		T23	1		T24	1
all_pins[19]	1640323	1			T22	157		T23	1		T24	1
all_pins[20]	1640323	1			T22	157		T23	1		T24	1
all_pins[21]	1640323	1			T22	157		T23	1		T24	1
all_pins[22]	1640323	1			T22	157		T23	1		T24	1
all_pins[23]	1640323	1			T22	157		T23	1		T24	1
all_pins[24]	1640323	1			T22	157		T23	1		T24	1
all_pins[25]	1640323	1			T22	157		T23	1		T24	1
all_pins[26]	1640323	1			T22	157		T23	1		T24	1
all_pins[27]	1640323	1			T22	157		T23	1		T24	1
all_pins[28]	1640323	1			T22	157		T23	1		T24	1
all_pins[29]	1640323	1			T22	157		T23	1		T24	1
all_pins[30]	1640323	1			T22	157		T23	1		T24	1
all_pins[31]	1640323	1			T22	157		T23	1		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	32649248	1			T22	3038		T23	32		T24	32
values[0x1]	19841088	1			T22	1986		T1	6626		T12	430
transitions[0x0=>0x1]	11880003	1			T22	1224		T1	4022		T12	304
transitions[0x1=>0x0]	11879849	1			T22	1224		T1	4021		T12	304

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1018548	1			T22	83		T23	1		T24	1
all_pins[0]	values[0x1]	621775	1			T22	74		T1	280		T12	8
all_pins[0]	transitions[0x0=>0x1]	384372	1			T22	45		T1	145		T12	6
all_pins[0]	transitions[0x1=>0x0]	383597	1			T22	46		T1	114		T12	6
all_pins[1]	values[0x0]	1018814	1			T22	86		T23	1		T24	1
all_pins[1]	values[0x1]	621509	1			T22	71		T1	254		T12	13
all_pins[1]	transitions[0x0=>0x1]	369662	1			T22	48		T1	107		T12	12
all_pins[1]	transitions[0x1=>0x0]	369928	1			T22	51		T1	133		T12	7
all_pins[2]	values[0x0]	1023211	1			T22	105		T23	1		T24	1
all_pins[2]	values[0x1]	617112	1			T22	52		T1	218		T12	8
all_pins[2]	transitions[0x0=>0x1]	367565	1			T22	39		T1	119		T12	8
all_pins[2]	transitions[0x1=>0x0]	371962	1			T22	58		T1	155		T12	13
all_pins[3]	values[0x0]	1020047	1			T22	89		T23	1		T24	1
all_pins[3]	values[0x1]	620276	1			T22	68		T1	224		T12	18
all_pins[3]	transitions[0x0=>0x1]	373404	1			T22	44		T1	106		T12	12
all_pins[3]	transitions[0x1=>0x0]	370240	1			T22	28		T1	100		T12	2
all_pins[4]	values[0x0]	1019816	1			T22	110		T23	1		T24	1
all_pins[4]	values[0x1]	620507	1			T22	47		T1	215		T12	17
all_pins[4]	transitions[0x0=>0x1]	371115	1			T22	24		T1	137		T12	12
all_pins[4]	transitions[0x1=>0x0]	370884	1			T22	45		T1	146		T12	13
all_pins[5]	values[0x0]	1020253	1			T22	77		T23	1		T24	1
all_pins[5]	values[0x1]	620070	1			T22	80		T1	239		T12	11
all_pins[5]	transitions[0x0=>0x1]	371082	1			T22	56		T1	170		T12	4
all_pins[5]	transitions[0x1=>0x0]	371519	1			T22	23		T1	146		T12	10
all_pins[6]	values[0x0]	1021218	1			T22	89		T23	1		T24	1
all_pins[6]	values[0x1]	619105	1			T22	68		T1	170		T12	12
all_pins[6]	transitions[0x0=>0x1]	369670	1			T22	39		T1	79		T12	9
all_pins[6]	transitions[0x1=>0x0]	370635	1			T22	51		T1	148		T12	8
all_pins[7]	values[0x0]	1021978	1			T22	82		T23	1		T24	1
all_pins[7]	values[0x1]	618345	1			T22	75		T1	199		T12	14
all_pins[7]	transitions[0x0=>0x1]	371238	1			T22	42		T1	130		T12	7
all_pins[7]	transitions[0x1=>0x0]	371998	1			T22	35		T1	101		T12	5
all_pins[8]	values[0x0]	1018464	1			T22	110		T23	1		T24	1
all_pins[8]	values[0x1]	621859	1			T22	47		T1	184		T12	12
all_pins[8]	transitions[0x0=>0x1]	372663	1			T22	30		T1	119		T12	3
all_pins[8]	transitions[0x1=>0x0]	369149	1			T22	58		T1	134		T12	5
all_pins[9]	values[0x0]	1023748	1			T22	106		T23	1		T24	1
all_pins[9]	values[0x1]	616575	1			T22	51		T1	187		T12	18
all_pins[9]	transitions[0x0=>0x1]	368653	1			T22	47		T1	131		T12	18
all_pins[9]	transitions[0x1=>0x0]	373937	1			T22	43		T1	128		T12	12
all_pins[10]	values[0x0]	1022166	1			T22	118		T23	1		T24	1
all_pins[10]	values[0x1]	618157	1			T22	39		T1	169		T12	18
all_pins[10]	transitions[0x0=>0x1]	373708	1			T22	31		T1	127		T12	11
all_pins[10]	transitions[0x1=>0x0]	372126	1			T22	43		T1	145		T12	11
all_pins[11]	values[0x0]	1020874	1			T22	79		T23	1		T24	1
all_pins[11]	values[0x1]	619449	1			T22	78		T1	212		T12	28
all_pins[11]	transitions[0x0=>0x1]	371911	1			T22	61		T1	132		T12	15
all_pins[11]	transitions[0x1=>0x0]	370619	1			T22	22		T1	89		T12	5
all_pins[12]	values[0x0]	1020401	1			T22	123		T23	1		T24	1
all_pins[12]	values[0x1]	619922	1			T22	34		T1	209		T12	18
all_pins[12]	transitions[0x0=>0x1]	370453	1			T22	16		T1	124		T12	12
all_pins[12]	transitions[0x1=>0x0]	369980	1			T22	60		T1	127		T12	22
all_pins[13]	values[0x0]	1021265	1			T22	111		T23	1		T24	1
all_pins[13]	values[0x1]	619058	1			T22	46		T1	230		T12	9
all_pins[13]	transitions[0x0=>0x1]	371262	1			T22	34		T1	149		T12	9
all_pins[13]	transitions[0x1=>0x0]	372126	1			T22	22		T1	128		T12	18
all_pins[14]	values[0x0]	1018390	1			T22	100		T23	1		T24	1
all_pins[14]	values[0x1]	621933	1			T22	57		T1	243		T12	5
all_pins[14]	transitions[0x0=>0x1]	372574	1			T22	42		T1	149		T12	4
all_pins[14]	transitions[0x1=>0x0]	369699	1			T22	31		T1	136		T12	8
all_pins[15]	values[0x0]	1017572	1			T22	102		T23	1		T24	1
all_pins[15]	values[0x1]	622751	1			T22	55		T1	159		T12	11
all_pins[15]	transitions[0x0=>0x1]	371633	1			T22	35		T1	80		T12	9
all_pins[15]	transitions[0x1=>0x0]	370815	1			T22	37		T1	164		T12	3
all_pins[16]	values[0x0]	1021349	1			T22	76		T23	1		T24	1
all_pins[16]	values[0x1]	618974	1			T22	81		T1	136		T12	6
all_pins[16]	transitions[0x0=>0x1]	370165	1			T22	46		T1	79		T12	6
all_pins[16]	transitions[0x1=>0x0]	373942	1			T22	20		T1	102		T12	11
all_pins[17]	values[0x0]	1017344	1			T22	99		T23	1		T24	1
all_pins[17]	values[0x1]	622979	1			T22	58		T1	220		T12	6
all_pins[17]	transitions[0x0=>0x1]	372765	1			T22	28		T1	168		T12	6
all_pins[17]	transitions[0x1=>0x0]	368760	1			T22	51		T1	84		T12	6
all_pins[18]	values[0x0]	1020979	1			T22	100		T23	1		T24	1
all_pins[18]	values[0x1]	619344	1			T22	57		T1	197		T12	14
all_pins[18]	transitions[0x0=>0x1]	370025	1			T22	31		T1	131		T12	14
all_pins[18]	transitions[0x1=>0x0]	373660	1			T22	32		T1	154		T12	6
all_pins[19]	values[0x0]	1023105	1			T22	106		T23	1		T24	1
all_pins[19]	values[0x1]	617218	1			T22	51		T1	242		T12	13
all_pins[19]	transitions[0x0=>0x1]	368649	1			T22	28		T1	135		T12	8
all_pins[19]	transitions[0x1=>0x0]	370775	1			T22	34		T1	90		T12	9
all_pins[20]	values[0x0]	1016559	1			T22	96		T23	1		T24	1
all_pins[20]	values[0x1]	623764	1			T22	61		T1	144		T12	16
all_pins[20]	transitions[0x0=>0x1]	372998	1			T22	34		T1	72		T12	10
all_pins[20]	transitions[0x1=>0x0]	366452	1			T22	24		T1	170		T12	7
all_pins[21]	values[0x0]	1016211	1			T22	65		T23	1		T24	1
all_pins[21]	values[0x1]	624112	1			T22	92		T1	204		T12	24
all_pins[21]	transitions[0x0=>0x1]	372277	1			T22	50		T1	146		T12	15
all_pins[21]	transitions[0x1=>0x0]	371929	1			T22	19		T1	86		T12	7
all_pins[22]	values[0x0]	1022155	1			T22	111		T23	1		T24	1
all_pins[22]	values[0x1]	618168	1			T22	46		T1	209		T12	11
all_pins[22]	transitions[0x0=>0x1]	367217	1			T22	17		T1	157		T12	6
all_pins[22]	transitions[0x1=>0x0]	373161	1			T22	63		T1	152		T12	19
all_pins[23]	values[0x0]	1018953	1			T22	87		T23	1		T24	1
all_pins[23]	values[0x1]	621370	1			T22	70		T1	167		T12	11
all_pins[23]	transitions[0x0=>0x1]	372944	1			T22	45		T1	101		T12	11
all_pins[23]	transitions[0x1=>0x0]	369742	1			T22	21		T1	143		T12	11
all_pins[24]	values[0x0]	1020897	1			T22	109		T23	1		T24	1
all_pins[24]	values[0x1]	619426	1			T22	48		T1	216		T12	14
all_pins[24]	transitions[0x0=>0x1]	369468	1			T22	21		T1	168		T12	14
all_pins[24]	transitions[0x1=>0x0]	371412	1			T22	43		T1	119		T12	11
all_pins[25]	values[0x0]	1021944	1			T22	108		T23	1		T24	1
all_pins[25]	values[0x1]	618379	1			T22	49		T1	180		T12	14
all_pins[25]	transitions[0x0=>0x1]	369282	1			T22	38		T1	110		T12	11
all_pins[25]	transitions[0x1=>0x0]	370329	1			T22	37		T1	146		T12	11
all_pins[26]	values[0x0]	1021742	1			T22	84		T23	1		T24	1
all_pins[26]	values[0x1]	618581	1			T22	73		T1	223		T12	10
all_pins[26]	transitions[0x0=>0x1]	370728	1			T22	52		T1	126		T12	8
all_pins[26]	transitions[0x1=>0x0]	370526	1			T22	28		T1	83		T12	12
all_pins[27]	values[0x0]	1019967	1			T22	79		T23	1		T24	1
all_pins[27]	values[0x1]	620356	1			T22	78		T1	191		T12	4
all_pins[27]	transitions[0x0=>0x1]	370143	1			T22	45		T1	107		T12	4
all_pins[27]	transitions[0x1=>0x0]	368368	1			T22	40		T1	139		T12	10
all_pins[28]	values[0x0]	1019144	1			T22	70		T23	1		T24	1
all_pins[28]	values[0x1]	621179	1			T22	87		T1	230		T12	20
all_pins[28]	transitions[0x0=>0x1]	371389	1			T22	42		T1	147		T12	18
all_pins[28]	transitions[0x1=>0x0]	370566	1			T22	33		T1	108		T12	2
all_pins[29]	values[0x0]	1019337	1			T22	112		T23	1		T24	1
all_pins[29]	values[0x1]	620986	1			T22	45		T1	243		T12	19
all_pins[29]	transitions[0x0=>0x1]	371289	1			T22	28		T1	117		T12	9
all_pins[29]	transitions[0x1=>0x0]	371482	1			T22	70		T1	104		T12	10
all_pins[30]	values[0x0]	1023628	1			T22	84		T23	1		T24	1
all_pins[30]	values[0x1]	616695	1			T22	73		T1	182		T12	20
all_pins[30]	transitions[0x0=>0x1]	366727	1			T22	57		T1	86		T12	7
all_pins[30]	transitions[0x1=>0x0]	371018	1			T22	29		T1	147		T12	6
all_pins[31]	values[0x0]	1019169	1			T22	82		T23	1		T24	1
all_pins[31]	values[0x1]	621154	1			T22	75		T1	250		T12	8
all_pins[31]	transitions[0x0=>0x1]	372972	1			T22	29		T1	168		T12	6
all_pins[31]	transitions[0x1=>0x0]	368513	1			T22	27		T1	100		T12	18