Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6654448	1			T22	257		T23	314		T24	227
all_values[1]	6654448	1			T22	257		T23	314		T24	227
all_values[2]	6654448	1			T22	257		T23	314		T24	227
all_values[3]	6654448	1			T22	257		T23	314		T24	227
all_values[4]	6654448	1			T22	257		T23	314		T24	227
all_values[5]	6654448	1			T22	257		T23	314		T24	227
all_values[6]	6654448	1			T22	257		T23	314		T24	227
all_values[7]	6654448	1			T22	257		T23	314		T24	227
all_values[8]	6654448	1			T22	257		T23	314		T24	227
all_values[9]	6654448	1			T22	257		T23	314		T24	227
all_values[10]	6654448	1			T22	257		T23	314		T24	227
all_values[11]	6654448	1			T22	257		T23	314		T24	227
all_values[12]	6654448	1			T22	257		T23	314		T24	227
all_values[13]	6654448	1			T22	257		T23	314		T24	227
all_values[14]	6654448	1			T22	257		T23	314		T24	227
all_values[15]	6654448	1			T22	257		T23	314		T24	227
all_values[16]	6654448	1			T22	257		T23	314		T24	227
all_values[17]	6654448	1			T22	257		T23	314		T24	227
all_values[18]	6654448	1			T22	257		T23	314		T24	227
all_values[19]	6654448	1			T22	257		T23	314		T24	227
all_values[20]	6654448	1			T22	257		T23	314		T24	227
all_values[21]	6654448	1			T22	257		T23	314		T24	227
all_values[22]	6654448	1			T22	257		T23	314		T24	227
all_values[23]	6654448	1			T22	257		T23	314		T24	227
all_values[24]	6654448	1			T22	257		T23	314		T24	227
all_values[25]	6654448	1			T22	257		T23	314		T24	227
all_values[26]	6654448	1			T22	257		T23	314		T24	227
all_values[27]	6654448	1			T22	257		T23	314		T24	227
all_values[28]	6654448	1			T22	257		T23	314		T24	227
all_values[29]	6654448	1			T22	257		T23	314		T24	227
all_values[30]	6654448	1			T22	257		T23	314		T24	227
all_values[31]	6654448	1			T22	257		T23	314		T24	227

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141726356

1

T22

3999

T23

10048

T24

7264

auto[1]

71215980

1

T22

4225

T1

24292

T12

1397

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84319175

1

T22

1367

T23

10048

T24

7264

auto[1]

128623161

1

T22

6857

T1

42331

T12

1805

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210924181

1

T22

8224

T23

10048

T24

7264

auto[1]

2018155

1

T1

1676

T12

241

T13

1385

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2409701	1			T22	14		T23	314		T24	227
all_values[0]	auto[0]	auto[0]	auto[1]	1970470	1			T22	95		T1	556		T12	29
all_values[0]	auto[0]	auto[1]	auto[0]	229505	1			T22	24		T1	64		T12	34
all_values[0]	auto[0]	auto[1]	auto[1]	1981612	1			T22	124		T1	782		T12	12
all_values[0]	auto[1]	auto[0]	auto[1]	31694	1			T1	21		T12	8		T13	19
all_values[0]	auto[1]	auto[1]	auto[1]	31466	1			T1	28		T12	2		T13	21
all_values[1]	auto[0]	auto[0]	auto[0]	2411727	1			T22	14		T23	314		T24	227
all_values[1]	auto[0]	auto[0]	auto[1]	1988181	1			T22	99		T1	497		T12	48
all_values[1]	auto[0]	auto[1]	auto[0]	225804	1			T22	17		T1	120		T12	7
all_values[1]	auto[0]	auto[1]	auto[1]	1965746	1			T22	127		T1	726		T12	19
all_values[1]	auto[1]	auto[0]	auto[1]	31823	1			T1	26		T12	5		T13	18
all_values[1]	auto[1]	auto[1]	auto[1]	31167	1			T1	33		T12	2		T13	33
all_values[2]	auto[0]	auto[0]	auto[0]	2411308	1			T22	25		T23	314		T24	227
all_values[2]	auto[0]	auto[0]	auto[1]	2004479	1			T22	100		T1	496		T12	32
all_values[2]	auto[0]	auto[1]	auto[0]	221839	1			T22	29		T1	143		T12	41
all_values[2]	auto[0]	auto[1]	auto[1]	1953908	1			T22	103		T1	698		T12	10
all_values[2]	auto[1]	auto[0]	auto[1]	32000	1			T1	23		T12	4		T13	21
all_values[2]	auto[1]	auto[1]	auto[1]	30914	1			T1	34		T12	2		T13	25
all_values[3]	auto[0]	auto[0]	auto[0]	2409388	1			T22	39		T23	314		T24	227
all_values[3]	auto[0]	auto[0]	auto[1]	1984836	1			T22	59		T1	530		T12	26
all_values[3]	auto[0]	auto[1]	auto[0]	222538	1			T22	34		T1	110		T12	11
all_values[3]	auto[0]	auto[1]	auto[1]	1974620	1			T22	125		T1	701		T12	30
all_values[3]	auto[1]	auto[0]	auto[1]	31588	1			T1	30		T12	4		T13	27
all_values[3]	auto[1]	auto[1]	auto[1]	31478	1			T1	24		T12	2		T13	18
all_values[4]	auto[0]	auto[0]	auto[0]	2410599	1			T22	30		T23	314		T24	227
all_values[4]	auto[0]	auto[0]	auto[1]	1999497	1			T22	116		T1	719		T12	25
all_values[4]	auto[0]	auto[1]	auto[0]	222169	1			T22	20		T1	44		T12	31
all_values[4]	auto[0]	auto[1]	auto[1]	1958799	1			T22	91		T1	592		T12	20
all_values[4]	auto[1]	auto[0]	auto[1]	32035	1			T1	36		T12	2		T13	23
all_values[4]	auto[1]	auto[1]	auto[1]	31349	1			T1	28		T12	5		T13	17
all_values[5]	auto[0]	auto[0]	auto[0]	2411844	1			T22	12		T23	314		T24	227
all_values[5]	auto[0]	auto[0]	auto[1]	1987605	1			T22	87		T1	553		T12	38
all_values[5]	auto[0]	auto[1]	auto[0]	227123	1			T22	16		T1	106		T12	21
all_values[5]	auto[0]	auto[1]	auto[1]	1964959	1			T22	142		T1	730		T12	24
all_values[5]	auto[1]	auto[0]	auto[1]	31884	1			T1	17		T12	5		T13	20
all_values[5]	auto[1]	auto[1]	auto[1]	31033	1			T1	29		T12	1		T13	25
all_values[6]	auto[0]	auto[0]	auto[0]	2408662	1			T22	27		T23	314		T24	227
all_values[6]	auto[0]	auto[0]	auto[1]	1987742	1			T22	86		T1	698		T12	32
all_values[6]	auto[0]	auto[1]	auto[0]	223659	1			T22	29		T1	90		T12	34
all_values[6]	auto[0]	auto[1]	auto[1]	1971279	1			T22	115		T1	589		T12	14
all_values[6]	auto[1]	auto[0]	auto[1]	31820	1			T1	33		T12	4		T13	19
all_values[6]	auto[1]	auto[1]	auto[1]	31286	1			T1	17		T12	4		T13	22
all_values[7]	auto[0]	auto[0]	auto[0]	2410085	1			T22	26		T23	314		T24	227
all_values[7]	auto[0]	auto[0]	auto[1]	1995138	1			T22	64		T1	634		T12	39
all_values[7]	auto[0]	auto[1]	auto[0]	227828	1			T22	11		T1	63		T12	23
all_values[7]	auto[0]	auto[1]	auto[1]	1958251	1			T22	156		T1	647		T12	19
all_values[7]	auto[1]	auto[0]	auto[1]	31752	1			T1	26		T12	7		T13	20
all_values[7]	auto[1]	auto[1]	auto[1]	31394	1			T1	26		T12	3		T13	20
all_values[8]	auto[0]	auto[0]	auto[0]	2407544	1			T22	15		T23	314		T24	227
all_values[8]	auto[0]	auto[0]	auto[1]	1985428	1			T22	124		T1	614		T12	20
all_values[8]	auto[0]	auto[1]	auto[0]	226806	1			T22	29		T1	133		T12	11
all_values[8]	auto[0]	auto[1]	auto[1]	1971460	1			T22	89		T1	582		T12	16
all_values[8]	auto[1]	auto[0]	auto[1]	31948	1			T1	27		T12	6		T13	19
all_values[8]	auto[1]	auto[1]	auto[1]	31262	1			T1	25		T13	20		T16	4
all_values[9]	auto[0]	auto[0]	auto[0]	2409222	1			T22	17		T23	314		T24	227
all_values[9]	auto[0]	auto[0]	auto[1]	1997677	1			T22	133		T1	740		T12	18
all_values[9]	auto[0]	auto[1]	auto[0]	224518	1			T22	9		T1	76		T12	31
all_values[9]	auto[0]	auto[1]	auto[1]	1960219	1			T22	98		T1	534		T12	20
all_values[9]	auto[1]	auto[0]	auto[1]	31799	1			T1	28		T12	3		T13	19
all_values[9]	auto[1]	auto[1]	auto[1]	31013	1			T1	20		T12	3		T13	24
all_values[10]	auto[0]	auto[0]	auto[0]	2414862	1			T22	28		T23	314		T24	227
all_values[10]	auto[0]	auto[0]	auto[1]	1996895	1			T22	149		T1	676		T12	34
all_values[10]	auto[0]	auto[1]	auto[0]	227058	1			T22	17		T1	126		T12	13
all_values[10]	auto[0]	auto[1]	auto[1]	1952765	1			T22	63		T1	503		T12	23
all_values[10]	auto[1]	auto[0]	auto[1]	31695	1			T1	34		T12	8		T13	27
all_values[10]	auto[1]	auto[1]	auto[1]	31173	1			T1	26		T12	3		T13	18
all_values[11]	auto[0]	auto[0]	auto[0]	2409197	1			T22	24		T23	314		T24	227
all_values[11]	auto[0]	auto[0]	auto[1]	2001458	1			T22	89		T1	691		T12	19
all_values[11]	auto[0]	auto[1]	auto[0]	221136	1			T22	14		T1	53		T12	24
all_values[11]	auto[0]	auto[1]	auto[1]	1959851	1			T22	130		T1	629		T12	30
all_values[11]	auto[1]	auto[0]	auto[1]	31709	1			T1	30		T12	5		T13	20
all_values[11]	auto[1]	auto[1]	auto[1]	31097	1			T1	27		T12	5		T13	29
all_values[12]	auto[0]	auto[0]	auto[0]	2413749	1			T22	36		T23	314		T24	227
all_values[12]	auto[0]	auto[0]	auto[1]	1979990	1			T22	154		T1	577		T12	9
all_values[12]	auto[0]	auto[1]	auto[0]	223389	1			T22	2		T1	142		T12	27
all_values[12]	auto[0]	auto[1]	auto[1]	1974445	1			T22	65		T1	669		T12	27
all_values[12]	auto[1]	auto[0]	auto[1]	31733	1			T1	19		T12	5		T13	23
all_values[12]	auto[1]	auto[1]	auto[1]	31142	1			T1	25		T12	2		T13	25
all_values[13]	auto[0]	auto[0]	auto[0]	2410919	1			T22	30		T23	314		T24	227
all_values[13]	auto[0]	auto[0]	auto[1]	1986881	1			T22	123		T1	532		T12	20
all_values[13]	auto[0]	auto[1]	auto[0]	224021	1			T22	24		T1	96		T12	40
all_values[13]	auto[0]	auto[1]	auto[1]	1969287	1			T22	80		T1	737		T12	10
all_values[13]	auto[1]	auto[0]	auto[1]	31927	1			T1	18		T12	3		T13	33
all_values[13]	auto[1]	auto[1]	auto[1]	31413	1			T1	32		T12	1		T13	16
all_values[14]	auto[0]	auto[0]	auto[0]	2408815	1			T22	16		T23	314		T24	227
all_values[14]	auto[0]	auto[0]	auto[1]	1993346	1			T22	136		T1	694		T12	34
all_values[14]	auto[0]	auto[1]	auto[0]	221674	1			T22	14		T1	64		T12	4
all_values[14]	auto[0]	auto[1]	auto[1]	1967497	1			T22	91		T1	659		T12	8
all_values[14]	auto[1]	auto[0]	auto[1]	31882	1			T1	30		T12	10		T13	12
all_values[14]	auto[1]	auto[1]	auto[1]	31234	1			T1	27		T12	1		T13	23
all_values[15]	auto[0]	auto[0]	auto[0]	2409746	1			T22	22		T23	314		T24	227
all_values[15]	auto[0]	auto[0]	auto[1]	1978626	1			T22	106		T1	740		T12	38
all_values[15]	auto[0]	auto[1]	auto[0]	225577	1			T22	31		T1	96		T12	6
all_values[15]	auto[0]	auto[1]	auto[1]	1977017	1			T22	98		T1	503		T12	15
all_values[15]	auto[1]	auto[0]	auto[1]	32004	1			T1	37		T12	3		T13	26
all_values[15]	auto[1]	auto[1]	auto[1]	31478	1			T1	23		T12	3		T13	17
all_values[16]	auto[0]	auto[0]	auto[0]	2411077	1			T22	4		T23	314		T24	227
all_values[16]	auto[0]	auto[0]	auto[1]	1987260	1			T22	85		T1	791		T12	37
all_values[16]	auto[0]	auto[1]	auto[0]	223583	1			T22	21		T1	87		T12	9
all_values[16]	auto[0]	auto[1]	auto[1]	1969223	1			T22	147		T1	461		T12	8
all_values[16]	auto[1]	auto[0]	auto[1]	31918	1			T1	37		T12	5		T13	21
all_values[16]	auto[1]	auto[1]	auto[1]	31387	1			T1	19		T13	17		T16	1
all_values[17]	auto[0]	auto[0]	auto[0]	2408731	1			T22	25		T23	314		T24	227
all_values[17]	auto[0]	auto[0]	auto[1]	1975298	1			T22	120		T1	620		T12	32
all_values[17]	auto[0]	auto[1]	auto[0]	221682	1			T22	14		T1	68		T12	12
all_values[17]	auto[0]	auto[1]	auto[1]	1986010	1			T22	98		T1	702		T12	13
all_values[17]	auto[1]	auto[0]	auto[1]	31440	1			T1	28		T12	4		T13	15
all_values[17]	auto[1]	auto[1]	auto[1]	31287	1			T1	24		T12	1		T13	25
all_values[18]	auto[0]	auto[0]	auto[0]	2414012	1			T22	29		T23	314		T24	227
all_values[18]	auto[0]	auto[0]	auto[1]	1989587	1			T22	76		T1	648		T12	42
all_values[18]	auto[0]	auto[1]	auto[0]	221372	1			T22	36		T1	73		T12	24
all_values[18]	auto[0]	auto[1]	auto[1]	1966550	1			T22	116		T1	622		T12	18
all_values[18]	auto[1]	auto[0]	auto[1]	31848	1			T1	26		T12	6		T13	30
all_values[18]	auto[1]	auto[1]	auto[1]	31079	1			T1	26		T12	2		T13	9
all_values[19]	auto[0]	auto[0]	auto[0]	2414393	1			T22	14		T23	314		T24	227
all_values[19]	auto[0]	auto[0]	auto[1]	1996373	1			T22	120		T1	641		T12	42
all_values[19]	auto[0]	auto[1]	auto[0]	219370	1			T22	15		T1	36		T12	18
all_values[19]	auto[0]	auto[1]	auto[1]	1961446	1			T22	108		T1	677		T12	20
all_values[19]	auto[1]	auto[0]	auto[1]	31997	1			T1	19		T12	3		T13	25
all_values[19]	auto[1]	auto[1]	auto[1]	30869	1			T1	26		T12	2		T13	31
all_values[20]	auto[0]	auto[0]	auto[0]	2405634	1			T22	38		T23	314		T24	227
all_values[20]	auto[0]	auto[0]	auto[1]	1985758	1			T22	90		T1	693		T12	21
all_values[20]	auto[0]	auto[1]	auto[0]	222789	1			T22	28		T1	112		T12	19
all_values[20]	auto[0]	auto[1]	auto[1]	1977052	1			T22	101		T1	519		T12	26
all_values[20]	auto[1]	auto[0]	auto[1]	31690	1			T1	27		T12	6		T13	28
all_values[20]	auto[1]	auto[1]	auto[1]	31525	1			T1	19		T12	1		T13	20
all_values[21]	auto[0]	auto[0]	auto[0]	2406229	1			T22	13		T23	314		T24	227
all_values[21]	auto[0]	auto[0]	auto[1]	1982256	1			T22	76		T1	550		T12	23
all_values[21]	auto[0]	auto[1]	auto[0]	226204	1			T22	12		T1	103		T12	29
all_values[21]	auto[0]	auto[1]	auto[1]	1976787	1			T22	156		T1	692		T12	30
all_values[21]	auto[1]	auto[0]	auto[1]	31702	1			T1	26		T12	6		T13	31
all_values[21]	auto[1]	auto[1]	auto[1]	31270	1			T1	29		T12	5		T13	17
all_values[22]	auto[0]	auto[0]	auto[0]	2411889	1			T22	50		T23	314		T24	227
all_values[22]	auto[0]	auto[0]	auto[1]	1982433	1			T22	83		T1	721		T12	45
all_values[22]	auto[0]	auto[1]	auto[0]	227387	1			T22	45		T1	48		T12	17
all_values[22]	auto[0]	auto[1]	auto[1]	1970046	1			T22	79		T1	603		T12	13
all_values[22]	auto[1]	auto[0]	auto[1]	31777	1			T1	30		T12	5		T13	24
all_values[22]	auto[1]	auto[1]	auto[1]	30916	1			T1	27		T12	1		T13	20
all_values[23]	auto[0]	auto[0]	auto[0]	2412351	1			T22	19		T23	314		T24	227
all_values[23]	auto[0]	auto[0]	auto[1]	1986844	1			T22	75		T1	848		T12	37
all_values[23]	auto[0]	auto[1]	auto[0]	223454	1			T22	33		T1	73		T12	17
all_values[23]	auto[0]	auto[1]	auto[1]	1968903	1			T22	130		T1	484		T12	19
all_values[23]	auto[1]	auto[0]	auto[1]	31701	1			T1	28		T12	6		T13	15
all_values[23]	auto[1]	auto[1]	auto[1]	31195	1			T1	19		T12	1		T13	19
all_values[24]	auto[0]	auto[0]	auto[0]	2410526	1			T22	9		T23	314		T24	227
all_values[24]	auto[0]	auto[0]	auto[1]	1984539	1			T22	146		T1	512		T12	33
all_values[24]	auto[0]	auto[1]	auto[0]	225730	1			T22	18		T1	109		T12	20
all_values[24]	auto[0]	auto[1]	auto[1]	1970590	1			T22	84		T1	711		T12	17
all_values[24]	auto[1]	auto[0]	auto[1]	31863	1			T1	32		T12	4		T13	23
all_values[24]	auto[1]	auto[1]	auto[1]	31200	1			T1	25		T12	3		T13	19
all_values[25]	auto[0]	auto[0]	auto[0]	2411194	1			T22	20		T23	314		T24	227
all_values[25]	auto[0]	auto[0]	auto[1]	1996405	1			T22	131		T1	717		T12	36
all_values[25]	auto[0]	auto[1]	auto[0]	225334	1			T22	16		T1	70		T12	15
all_values[25]	auto[0]	auto[1]	auto[1]	1958442	1			T22	90		T1	595		T12	20
all_values[25]	auto[1]	auto[0]	auto[1]	31653	1			T1	24		T12	9		T13	37
all_values[25]	auto[1]	auto[1]	auto[1]	31420	1			T1	24		T12	2		T13	11
all_values[26]	auto[0]	auto[0]	auto[0]	2409577	1			T22	10		T23	314		T24	227
all_values[26]	auto[0]	auto[0]	auto[1]	1978880	1			T22	99		T1	540		T12	33
all_values[26]	auto[0]	auto[1]	auto[0]	225882	1			T22	20		T1	134		T12	24
all_values[26]	auto[0]	auto[1]	auto[1]	1976889	1			T22	128		T1	686		T12	20
all_values[26]	auto[1]	auto[0]	auto[1]	32169	1			T1	19		T12	4		T13	31
all_values[26]	auto[1]	auto[1]	auto[1]	31051	1			T1	39		T12	5		T13	17
all_values[27]	auto[0]	auto[0]	auto[0]	2409241	1			T22	17		T23	314		T24	227
all_values[27]	auto[0]	auto[0]	auto[1]	1969129	1			T22	87		T1	612		T12	28
all_values[27]	auto[0]	auto[1]	auto[0]	227300	1			T22	11		T1	102		T12	36
all_values[27]	auto[0]	auto[1]	auto[1]	1985673	1			T22	142		T1	632		T12	3
all_values[27]	auto[1]	auto[0]	auto[1]	31922	1			T1	28		T12	6		T13	24
all_values[27]	auto[1]	auto[1]	auto[1]	31183	1			T1	20		T12	2		T13	17
all_values[28]	auto[0]	auto[0]	auto[0]	2411235	1			T22	26		T23	314		T24	227
all_values[28]	auto[0]	auto[0]	auto[1]	1977818	1			T22	67		T1	595		T12	28
all_values[28]	auto[0]	auto[1]	auto[0]	224682	1			T22	9		T1	71		T12	20
all_values[28]	auto[0]	auto[1]	auto[1]	1977678	1			T22	155		T1	740		T12	29
all_values[28]	auto[1]	auto[0]	auto[1]	31484	1			T1	20		T12	5		T13	22
all_values[28]	auto[1]	auto[1]	auto[1]	31551	1			T1	28		T12	1		T13	19
all_values[29]	auto[0]	auto[0]	auto[0]	2412514	1			T22	22		T23	314		T24	227
all_values[29]	auto[0]	auto[0]	auto[1]	1969587	1			T22	144		T1	453		T12	23
all_values[29]	auto[0]	auto[1]	auto[0]	224438	1			T22	17		T1	115		T12	37
all_values[29]	auto[0]	auto[1]	auto[1]	1984725	1			T22	74		T1	834		T12	25
all_values[29]	auto[1]	auto[0]	auto[1]	31764	1			T1	17		T12	5		T13	22
all_values[29]	auto[1]	auto[1]	auto[1]	31420	1			T1	34		T12	4		T13	18
all_values[30]	auto[0]	auto[0]	auto[0]	2406485	1			T22	28		T23	314		T24	227
all_values[30]	auto[0]	auto[0]	auto[1]	1991439	1			T22	75		T1	768		T12	14
all_values[30]	auto[0]	auto[1]	auto[0]	221813	1			T22	22		T1	118		T12	41
all_values[30]	auto[0]	auto[1]	auto[1]	1971546	1			T22	132		T1	470		T12	25
all_values[30]	auto[1]	auto[0]	auto[1]	32131	1			T1	26		T12	4		T13	22
all_values[30]	auto[1]	auto[1]	auto[1]	31034	1			T1	20		T12	6		T13	16
all_values[31]	auto[0]	auto[0]	auto[0]	2411170	1			T22	22		T23	314		T24	227
all_values[31]	auto[0]	auto[0]	auto[1]	1982359	1			T22	84		T1	512		T12	36
all_values[31]	auto[0]	auto[1]	auto[0]	229885	1			T22	9		T1	128		T12	31
all_values[31]	auto[0]	auto[1]	auto[1]	1967517	1			T22	142		T1	778		T12	10
all_values[31]	auto[1]	auto[0]	auto[1]	32164	1			T1	22		T12	4		T13	19
all_values[31]	auto[1]	auto[1]	auto[1]	31353	1			T1	29		T12	2		T13	22

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal