Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[1]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[2]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[3]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[4]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[5]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[6]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[7]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[8]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[9]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[10]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[11]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[12]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[13]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[14]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[15]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[16]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[17]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[18]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[19]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[20]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[21]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[22]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[23]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[24]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[25]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[26]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[27]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[28]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[29]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[30]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[31]	6621731	1			T22	109		T23	601		T24	313

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115984197

1

T22

1755

T23

14758

T24

6348

auto[1]

95911195

1

T22

1733

T23

4474

T24

3668

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

175535639

1

T22

3488

T23

13324

T24

7322

auto[1]

36359753

1

T23

5908

T24

2694

T25

5822

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164947729

1

T22

3488

T23

9464

T24

7155

auto[1]

46947663

1

T23

9768

T24

2861

T25

5990

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2445832	1			T22	65		T23	221		T24	96
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2139918	1			T22	44		T23	23		T24	81
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	570306	1			T23	126		T24	32		T25	86
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	601972	1			T23	125		T24	60		T26	50
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	297449	1			T23	18		T25	106		T1	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	566254	1			T23	88		T24	44		T25	94
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2445411	1			T22	45		T23	212		T24	109
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2133769	1			T22	64		T23	38		T24	73
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	569957	1			T23	78		T24	39		T25	67
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	607259	1			T23	167		T24	34		T26	69
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	297124	1			T23	12		T25	138		T1	10
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	568211	1			T23	94		T24	58		T25	78
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2444754	1			T22	51		T23	136		T24	104
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2133761	1			T22	58		T23	33		T24	68
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	568735	1			T23	93		T24	50		T25	82
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	605529	1			T23	200		T24	45		T26	56
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	297829	1			T23	21		T25	112		T1	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	571123	1			T23	118		T24	46		T25	83
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2458757	1			T22	50		T23	142		T24	113
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2126839	1			T22	59		T23	17		T24	63
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	572087	1			T23	103		T24	37		T25	88
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	599105	1			T23	199		T24	56		T26	30
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	297662	1			T23	32		T25	119		T1	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	567281	1			T23	108		T24	44		T25	104
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2450071	1			T22	64		T23	169		T24	120
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2131977	1			T22	45		T23	22		T24	62
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	567404	1			T23	94		T24	48		T25	72
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	605764	1			T23	168		T24	51		T26	51
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	298899	1			T23	23		T25	94		T1	17
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	567616	1			T23	125		T24	32		T25	129
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2457246	1			T22	55		T23	250		T24	113
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2128879	1			T22	54		T23	29		T24	69
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	572717	1			T23	110		T24	48		T25	80
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	601415	1			T23	129		T24	50		T26	52
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	296987	1			T23	16		T25	123		T1	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	564487	1			T23	67		T24	33		T25	80
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2450883	1			T22	57		T23	158		T24	114
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2132239	1			T22	52		T23	22		T24	82
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	573012	1			T23	112		T24	53		T25	82
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	601882	1			T23	171		T24	36		T26	67
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	295649	1			T23	25		T25	89		T1	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	568066	1			T23	113		T24	28		T25	114
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2447825	1			T22	48		T23	207		T24	127
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2131676	1			T22	61		T23	24		T24	73
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	573403	1			T23	116		T24	30		T25	108
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	604171	1			T23	170		T24	57		T26	28
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	296505	1			T23	17		T25	86		T1	15
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	568151	1			T23	67		T24	26		T25	97
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2456514	1			T22	59		T23	172		T24	100
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2130632	1			T22	50		T23	29		T24	72
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	569957	1			T23	80		T24	30		T25	83
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	603464	1			T23	197		T24	64		T26	58
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	297077	1			T23	25		T25	78		T1	19
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	564087	1			T23	98		T24	47		T25	106
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2437863	1			T22	65		T23	134		T24	114
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2146615	1			T22	44		T23	8		T24	70
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	571684	1			T23	82		T24	33		T25	86
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	603126	1			T23	209		T24	32		T26	76
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	295859	1			T23	31		T25	73		T1	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	566584	1			T23	137		T24	64		T25	106
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2449080	1			T22	57		T23	200		T24	107
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2131296	1			T22	52		T23	29		T24	77
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	568679	1			T23	125		T24	38		T25	92
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	604398	1			T23	179		T24	44		T26	53
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	299550	1			T23	18		T25	91		T1	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	568728	1			T23	50		T24	47		T25	88
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2452231	1			T22	50		T23	165		T24	95
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2126571	1			T22	59		T23	26		T24	80
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	571164	1			T23	116		T24	42		T25	118
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	606088	1			T23	173		T24	62		T26	60
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	298250	1			T23	27		T25	74		T1	18
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	567427	1			T23	94		T24	34		T25	82
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2446703	1			T22	52		T23	185		T24	112
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2138831	1			T22	57		T23	16		T24	68
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	572274	1			T23	65		T24	37		T25	74
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	600107	1			T23	218		T24	52		T26	80
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	296898	1			T23	24		T25	121		T1	16
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	566918	1			T23	93		T24	44		T25	82
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2456802	1			T22	44		T23	137		T24	111
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2123648	1			T22	65		T23	26		T24	71
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	571554	1			T23	61		T24	43		T25	74
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	601546	1			T23	232		T24	38		T26	52
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	298770	1			T23	22		T25	122		T1	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	569411	1			T23	123		T24	50		T25	70
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2448223	1			T22	63		T23	245		T24	110
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2134075	1			T22	46		T23	30		T24	75
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	570758	1			T23	112		T24	64		T25	75
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	604178	1			T23	142		T24	20		T26	35
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	296115	1			T23	11		T25	74		T1	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	568382	1			T23	61		T24	44		T25	86
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2459321	1			T22	43		T23	235		T24	105
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2119555	1			T22	66		T23	39		T24	83
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	572043	1			T23	83		T24	34		T25	90
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	602374	1			T23	151		T24	56		T26	57
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	298736	1			T23	9		T25	101		T1	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	569702	1			T23	84		T24	35		T25	78
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2449137	1			T22	54		T23	170		T24	104
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2135899	1			T22	55		T23	21		T24	68
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	569801	1			T23	125		T24	46		T25	99
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	604286	1			T23	186		T24	33		T26	60
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	298020	1			T23	32		T25	98		T1	15
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	564588	1			T23	67		T24	62		T25	78
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2456406	1			T22	66		T23	176		T24	121
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2130724	1			T22	43		T23	11		T24	68
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	567453	1			T23	56		T24	56		T25	90
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	606481	1			T23	247		T24	28		T26	60
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	298744	1			T23	33		T25	96		T1	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	561923	1			T23	78		T24	40		T25	79
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2446063	1			T22	46		T23	168		T24	93
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2142354	1			T22	63		T23	18		T24	79
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	570512	1			T23	53		T24	34		T25	102
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	603375	1			T23	240		T24	61		T26	32
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	294731	1			T23	33		T25	117		T1	16
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	564696	1			T23	89		T24	46		T25	62
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2456810	1			T22	53		T23	183		T24	108
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2132561	1			T22	56		T23	21		T24	76
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	570285	1			T23	72		T24	58		T25	106
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	600622	1			T23	185		T24	44		T26	42
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	299754	1			T23	35		T25	97		T1	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	561699	1			T23	105		T24	27		T25	94
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2456651	1			T22	58		T23	167		T24	110
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2131915	1			T22	51		T23	26		T24	73
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	567382	1			T23	58		T24	42		T25	90
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	604674	1			T23	213		T24	46		T26	38
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	297009	1			T23	21		T25	89		T1	25
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	564100	1			T23	116		T24	42		T25	110
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2452592	1			T22	54		T23	229		T24	122
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2133935	1			T22	55		T23	33		T24	69
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	568944	1			T23	114		T24	30		T25	84
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	604949	1			T23	167		T24	46		T26	48
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	296714	1			T23	16		T25	112		T1	18
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	564597	1			T23	42		T24	46		T25	88
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2447434	1			T22	59		T23	120		T24	105
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2137898	1			T22	50		T23	10		T24	71
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	569097	1			T23	94		T24	34		T25	90
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	605355	1			T23	223		T24	61		T26	67
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	297133	1			T23	28		T25	96		T1	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	564814	1			T23	126		T24	42		T25	99
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2440340	1			T22	54		T23	145		T24	112
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2145759	1			T22	55		T23	19		T24	68
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	573861	1			T23	122		T24	41		T25	104
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	603299	1			T23	202		T24	56		T26	64
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	294482	1			T23	33		T25	86		T1	25
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	563990	1			T23	80		T24	36		T25	89
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2449805	1			T22	49		T23	182		T24	128
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2139823	1			T22	60		T23	21		T24	69
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	570337	1			T23	95		T24	44		T25	91
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	601925	1			T23	192		T24	40		T26	74
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	295921	1			T23	19		T25	70		T1	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	563920	1			T23	92		T24	32		T25	102
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2457039	1			T22	61		T23	200		T24	114
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2133546	1			T22	48		T23	35		T24	74
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	570968	1			T23	70		T24	58		T25	77
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	601929	1			T23	222		T24	29		T26	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	293513	1			T23	12		T25	84		T1	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	564736	1			T23	62		T24	38		T25	104
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2452546	1			T22	62		T23	214		T24	117
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2135127	1			T22	47		T23	12		T24	69
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	568191	1			T23	86		T24	43		T25	87
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	603043	1			T23	179		T24	50		T26	40
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	298558	1			T23	15		T25	94		T1	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	564266	1			T23	95		T24	34		T25	86
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2445928	1			T22	55		T23	205		T24	110
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2136024	1			T22	54		T23	27		T24	68
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	569514	1			T23	108		T24	36		T25	118
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	606087	1			T23	147		T24	51		T26	28
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	297544	1			T23	10		T25	54		T1	18
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	566634	1			T23	104		T24	48		T25	106
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2446831	1			T22	42		T23	149		T24	117
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2136200	1			T22	67		T23	25		T24	69
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	571530	1			T23	53		T24	36		T25	94
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	602008	1			T23	210		T24	63		T26	41
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	299978	1			T23	18		T25	85		T1	13
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	565184	1			T23	146		T24	28		T25	82
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2457450	1			T22	67		T23	174		T24	115
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2129463	1			T22	42		T23	9		T24	66
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	567490	1			T23	89		T24	32		T25	102
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	605192	1			T23	212		T24	52		T26	52
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	298785	1			T23	39		T25	101		T1	11
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	563351	1			T23	78		T24	48		T25	102
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2447553	1			T22	50		T23	194		T24	98
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2134641	1			T22	59		T23	19		T24	76
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	567839	1			T23	81		T24	40		T25	101
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	606019	1			T23	180		T24	39		T26	48
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	298729	1			T23	23		T25	92		T1	23
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	566950	1			T23	104		T24	60		T25	100
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2447833	1			T22	57		T23	189		T24	99
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2136123	1			T22	52		T23	17		T24	73
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	568584	1			T23	64		T24	41		T25	102
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	607119	1			T23	194		T24	40		T26	40
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	297717	1			T23	29		T25	90		T1	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	564355	1			T23	108		T24	60		T25	70

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal