Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[1]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[2]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[3]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[4]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[5]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[6]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[7]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[8]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[9]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[10]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[11]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[12]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[13]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[14]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[15]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[16]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[17]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[18]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[19]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[20]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[21]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[22]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[23]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[24]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[25]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[26]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[27]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[28]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[29]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[30]	6621731	1			T22	109		T23	601		T24	313
bins_for_gpio_bits[31]	6621731	1			T22	109		T23	601		T24	313

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115984197

1

T22

1755

T23

14758

T24

6348

auto[1]

95911195

1

T22

1733

T23

4474

T24

3668

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115974819

1

T22

1755

T23

14758

T24

6343

auto[1]

95920573

1

T22

1733

T23

4474

T24

3673

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3516049	1			T22	65		T23	460		T24	174
bins_for_gpio_bits[0]	auto[0]	auto[1]	101741	1			T23	12		T24	14		T25	26
bins_for_gpio_bits[0]	auto[1]	auto[0]	102061	1			T23	12		T24	14		T25	26
bins_for_gpio_bits[0]	auto[1]	auto[1]	2901880	1			T22	44		T23	117		T24	111
bins_for_gpio_bits[1]	auto[0]	auto[0]	3520100	1			T22	45		T23	441		T24	172
bins_for_gpio_bits[1]	auto[0]	auto[1]	102190	1			T23	16		T24	10		T25	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	102527	1			T23	16		T24	10		T25	16
bins_for_gpio_bits[1]	auto[1]	auto[1]	2896914	1			T22	64		T23	128		T24	121
bins_for_gpio_bits[2]	auto[0]	auto[0]	3516223	1			T22	51		T23	410		T24	186
bins_for_gpio_bits[2]	auto[0]	auto[1]	102492	1			T23	19		T24	13		T25	21
bins_for_gpio_bits[2]	auto[1]	auto[0]	102795	1			T23	19		T24	13		T25	21
bins_for_gpio_bits[2]	auto[1]	auto[1]	2900221	1			T22	58		T23	153		T24	101
bins_for_gpio_bits[3]	auto[0]	auto[0]	3527862	1			T22	50		T23	425		T24	197
bins_for_gpio_bits[3]	auto[0]	auto[1]	101838	1			T23	19		T24	9		T25	23
bins_for_gpio_bits[3]	auto[1]	auto[0]	102087	1			T23	19		T24	9		T25	23
bins_for_gpio_bits[3]	auto[1]	auto[1]	2889944	1			T22	59		T23	138		T24	98
bins_for_gpio_bits[4]	auto[0]	auto[0]	3520623	1			T22	64		T23	414		T24	207
bins_for_gpio_bits[4]	auto[0]	auto[1]	102312	1			T23	17		T24	12		T25	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	102616	1			T23	17		T24	12		T25	24
bins_for_gpio_bits[4]	auto[1]	auto[1]	2896180	1			T22	45		T23	153		T24	82
bins_for_gpio_bits[5]	auto[0]	auto[0]	3529028	1			T22	55		T23	476		T24	199
bins_for_gpio_bits[5]	auto[0]	auto[1]	102061	1			T23	13		T24	11		T25	20
bins_for_gpio_bits[5]	auto[1]	auto[0]	102350	1			T23	13		T24	12		T25	20
bins_for_gpio_bits[5]	auto[1]	auto[1]	2888292	1			T22	54		T23	99		T24	91
bins_for_gpio_bits[6]	auto[0]	auto[0]	3523156	1			T22	57		T23	426		T24	193
bins_for_gpio_bits[6]	auto[0]	auto[1]	102363	1			T23	15		T24	10		T25	19
bins_for_gpio_bits[6]	auto[1]	auto[0]	102621	1			T23	15		T24	10		T25	19
bins_for_gpio_bits[6]	auto[1]	auto[1]	2893591	1			T22	52		T23	145		T24	100
bins_for_gpio_bits[7]	auto[0]	auto[0]	3522509	1			T22	48		T23	480		T24	205
bins_for_gpio_bits[7]	auto[0]	auto[1]	102584	1			T23	13		T24	9		T25	23
bins_for_gpio_bits[7]	auto[1]	auto[0]	102890	1			T23	13		T24	9		T25	23
bins_for_gpio_bits[7]	auto[1]	auto[1]	2893748	1			T22	61		T23	95		T24	90
bins_for_gpio_bits[8]	auto[0]	auto[0]	3527658	1			T22	59		T23	428		T24	182
bins_for_gpio_bits[8]	auto[0]	auto[1]	101981	1			T23	21		T24	11		T25	25
bins_for_gpio_bits[8]	auto[1]	auto[0]	102277	1			T23	21		T24	12		T25	24
bins_for_gpio_bits[8]	auto[1]	auto[1]	2889815	1			T22	50		T23	131		T24	108
bins_for_gpio_bits[9]	auto[0]	auto[0]	3510410	1			T22	65		T23	407		T24	169
bins_for_gpio_bits[9]	auto[0]	auto[1]	101976	1			T23	18		T24	10		T25	19
bins_for_gpio_bits[9]	auto[1]	auto[0]	102263	1			T23	18		T24	10		T25	19
bins_for_gpio_bits[9]	auto[1]	auto[1]	2907082	1			T22	44		T23	158		T24	124
bins_for_gpio_bits[10]	auto[0]	auto[0]	3519899	1			T22	57		T23	493		T24	176
bins_for_gpio_bits[10]	auto[0]	auto[1]	102004	1			T23	11		T24	12		T25	23
bins_for_gpio_bits[10]	auto[1]	auto[0]	102258	1			T23	11		T24	13		T25	23
bins_for_gpio_bits[10]	auto[1]	auto[1]	2897570	1			T22	52		T23	86		T24	112
bins_for_gpio_bits[11]	auto[0]	auto[0]	3526805	1			T22	50		T23	437		T24	189
bins_for_gpio_bits[11]	auto[0]	auto[1]	102401	1			T23	17		T24	10		T25	28
bins_for_gpio_bits[11]	auto[1]	auto[0]	102678	1			T23	17		T24	10		T25	28
bins_for_gpio_bits[11]	auto[1]	auto[1]	2889847	1			T22	59		T23	130		T24	104
bins_for_gpio_bits[12]	auto[0]	auto[0]	3516937	1			T22	52		T23	455		T24	190
bins_for_gpio_bits[12]	auto[0]	auto[1]	101865	1			T23	13		T24	11		T25	21
bins_for_gpio_bits[12]	auto[1]	auto[0]	102147	1			T23	13		T24	11		T25	21
bins_for_gpio_bits[12]	auto[1]	auto[1]	2900782	1			T22	57		T23	120		T24	101
bins_for_gpio_bits[13]	auto[0]	auto[0]	3527353	1			T22	44		T23	408		T24	178
bins_for_gpio_bits[13]	auto[0]	auto[1]	102251	1			T23	22		T24	14		T25	23
bins_for_gpio_bits[13]	auto[1]	auto[0]	102549	1			T23	22		T24	14		T25	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	2889578	1			T22	65		T23	149		T24	107
bins_for_gpio_bits[14]	auto[0]	auto[0]	3520408	1			T22	63		T23	486		T24	184
bins_for_gpio_bits[14]	auto[0]	auto[1]	102482	1			T23	13		T24	10		T25	17
bins_for_gpio_bits[14]	auto[1]	auto[0]	102751	1			T23	13		T24	10		T25	16
bins_for_gpio_bits[14]	auto[1]	auto[1]	2896090	1			T22	46		T23	89		T24	109
bins_for_gpio_bits[15]	auto[0]	auto[0]	3530815	1			T22	43		T23	456		T24	186
bins_for_gpio_bits[15]	auto[0]	auto[1]	102627	1			T23	13		T24	8		T25	23
bins_for_gpio_bits[15]	auto[1]	auto[0]	102923	1			T23	13		T24	9		T25	23
bins_for_gpio_bits[15]	auto[1]	auto[1]	2885366	1			T22	66		T23	119		T24	110
bins_for_gpio_bits[16]	auto[0]	auto[0]	3520413	1			T22	54		T23	470		T24	173
bins_for_gpio_bits[16]	auto[0]	auto[1]	102527	1			T23	11		T24	10		T25	25
bins_for_gpio_bits[16]	auto[1]	auto[0]	102811	1			T23	11		T24	10		T25	24
bins_for_gpio_bits[16]	auto[1]	auto[1]	2895980	1			T22	55		T23	109		T24	120
bins_for_gpio_bits[17]	auto[0]	auto[0]	3528058	1			T22	66		T23	463		T24	197
bins_for_gpio_bits[17]	auto[0]	auto[1]	102007	1			T23	16		T24	8		T25	24
bins_for_gpio_bits[17]	auto[1]	auto[0]	102282	1			T23	16		T24	8		T25	24
bins_for_gpio_bits[17]	auto[1]	auto[1]	2889384	1			T22	43		T23	106		T24	100
bins_for_gpio_bits[18]	auto[0]	auto[0]	3517192	1			T22	46		T23	442		T24	178
bins_for_gpio_bits[18]	auto[0]	auto[1]	102441	1			T23	19		T24	10		T25	22
bins_for_gpio_bits[18]	auto[1]	auto[0]	102758	1			T23	19		T24	10		T25	22
bins_for_gpio_bits[18]	auto[1]	auto[1]	2899340	1			T22	63		T23	121		T24	115
bins_for_gpio_bits[19]	auto[0]	auto[0]	3525849	1			T22	53		T23	427		T24	198
bins_for_gpio_bits[19]	auto[0]	auto[1]	101589	1			T23	13		T24	11		T25	25
bins_for_gpio_bits[19]	auto[1]	auto[0]	101868	1			T23	13		T24	12		T25	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	2892425	1			T22	56		T23	148		T24	92
bins_for_gpio_bits[20]	auto[0]	auto[0]	3526288	1			T22	58		T23	416		T24	184
bins_for_gpio_bits[20]	auto[0]	auto[1]	102117	1			T23	22		T24	14		T25	19
bins_for_gpio_bits[20]	auto[1]	auto[0]	102419	1			T23	22		T24	14		T25	19
bins_for_gpio_bits[20]	auto[1]	auto[1]	2890907	1			T22	51		T23	141		T24	101
bins_for_gpio_bits[21]	auto[0]	auto[0]	3523888	1			T22	54		T23	497		T24	187
bins_for_gpio_bits[21]	auto[0]	auto[1]	102293	1			T23	13		T24	11		T25	19
bins_for_gpio_bits[21]	auto[1]	auto[0]	102597	1			T23	13		T24	11		T25	19
bins_for_gpio_bits[21]	auto[1]	auto[1]	2892953	1			T22	55		T23	78		T24	104
bins_for_gpio_bits[22]	auto[0]	auto[0]	3519000	1			T22	59		T23	416		T24	190
bins_for_gpio_bits[22]	auto[0]	auto[1]	102572	1			T23	21		T24	10		T25	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	102886	1			T23	21		T24	10		T25	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	2897273	1			T22	50		T23	143		T24	103
bins_for_gpio_bits[23]	auto[0]	auto[0]	3514579	1			T22	54		T23	454		T24	197
bins_for_gpio_bits[23]	auto[0]	auto[1]	102627	1			T23	15		T24	12		T25	28
bins_for_gpio_bits[23]	auto[1]	auto[0]	102921	1			T23	15		T24	12		T25	28
bins_for_gpio_bits[23]	auto[1]	auto[1]	2901604	1			T22	55		T23	117		T24	92
bins_for_gpio_bits[24]	auto[0]	auto[0]	3519815	1			T22	49		T23	455		T24	203
bins_for_gpio_bits[24]	auto[0]	auto[1]	101938	1			T23	14		T24	9		T25	22
bins_for_gpio_bits[24]	auto[1]	auto[0]	102252	1			T23	14		T24	9		T25	21
bins_for_gpio_bits[24]	auto[1]	auto[1]	2897726	1			T22	60		T23	118		T24	92
bins_for_gpio_bits[25]	auto[0]	auto[0]	3527154	1			T22	61		T23	484		T24	191
bins_for_gpio_bits[25]	auto[0]	auto[1]	102467	1			T23	8		T24	10		T25	20
bins_for_gpio_bits[25]	auto[1]	auto[0]	102782	1			T23	8		T24	10		T25	19
bins_for_gpio_bits[25]	auto[1]	auto[1]	2889328	1			T22	48		T23	101		T24	102
bins_for_gpio_bits[26]	auto[0]	auto[0]	3521389	1			T22	62		T23	464		T24	200
bins_for_gpio_bits[26]	auto[0]	auto[1]	102076	1			T23	15		T24	10		T25	24
bins_for_gpio_bits[26]	auto[1]	auto[0]	102391	1			T23	15		T24	10		T25	23
bins_for_gpio_bits[26]	auto[1]	auto[1]	2895875	1			T22	47		T23	107		T24	93
bins_for_gpio_bits[27]	auto[0]	auto[0]	3518735	1			T22	55		T23	442		T24	184
bins_for_gpio_bits[27]	auto[0]	auto[1]	102512	1			T23	18		T24	13		T25	29
bins_for_gpio_bits[27]	auto[1]	auto[0]	102794	1			T23	18		T24	13		T25	29
bins_for_gpio_bits[27]	auto[1]	auto[1]	2897690	1			T22	54		T23	123		T24	103
bins_for_gpio_bits[28]	auto[0]	auto[0]	3518102	1			T22	42		T23	389		T24	205
bins_for_gpio_bits[28]	auto[0]	auto[1]	101977	1			T23	23		T24	11		T25	30
bins_for_gpio_bits[28]	auto[1]	auto[0]	102267	1			T23	23		T24	11		T25	30
bins_for_gpio_bits[28]	auto[1]	auto[1]	2899385	1			T22	67		T23	166		T24	86
bins_for_gpio_bits[29]	auto[0]	auto[0]	3527673	1			T22	67		T23	456		T24	188
bins_for_gpio_bits[29]	auto[0]	auto[1]	102166	1			T23	19		T24	11		T25	20
bins_for_gpio_bits[29]	auto[1]	auto[0]	102459	1			T23	19		T24	11		T25	20
bins_for_gpio_bits[29]	auto[1]	auto[1]	2889433	1			T22	42		T23	107		T24	103
bins_for_gpio_bits[30]	auto[0]	auto[0]	3518653	1			T22	50		T23	438		T24	164
bins_for_gpio_bits[30]	auto[0]	auto[1]	102454	1			T23	17		T24	13		T25	24
bins_for_gpio_bits[30]	auto[1]	auto[0]	102758	1			T23	17		T24	13		T25	23
bins_for_gpio_bits[30]	auto[1]	auto[1]	2897866	1			T22	59		T23	129		T24	123
bins_for_gpio_bits[31]	auto[0]	auto[0]	3521335	1			T22	57		T23	430		T24	168
bins_for_gpio_bits[31]	auto[0]	auto[1]	101930	1			T23	17		T24	12		T25	20
bins_for_gpio_bits[31]	auto[1]	auto[0]	102201	1			T23	17		T24	12		T25	20
bins_for_gpio_bits[31]	auto[1]	auto[1]	2896265	1			T22	52		T23	137		T24	121