Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4411865 |
1 |
|
|
T22 |
109 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2242583 |
1 |
|
|
T22 |
148 |
|
T1 |
874 |
|
T12 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6377738 |
1 |
|
|
T22 |
247 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
276710 |
1 |
|
|
T22 |
10 |
|
T1 |
29 |
|
T13 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4445825 |
1 |
|
|
T22 |
122 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2208623 |
1 |
|
|
T22 |
135 |
|
T1 |
740 |
|
T12 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
958775 |
1 |
|
|
T22 |
53 |
|
T1 |
314 |
|
T12 |
15 |
| auto[1] |
auto[0] |
auto[1] |
137470 |
1 |
|
|
T22 |
6 |
|
T1 |
15 |
|
T13 |
7 |
| auto[1] |
auto[1] |
auto[0] |
973138 |
1 |
|
|
T22 |
72 |
|
T1 |
397 |
|
T12 |
28 |
| auto[1] |
auto[1] |
auto[1] |
139240 |
1 |
|
|
T22 |
4 |
|
T1 |
14 |
|
T13 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4431731 |
1 |
|
|
T22 |
113 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2222717 |
1 |
|
|
T22 |
144 |
|
T1 |
879 |
|
T12 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373837 |
1 |
|
|
T22 |
253 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280611 |
1 |
|
|
T22 |
4 |
|
T1 |
28 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420608 |
1 |
|
|
T22 |
171 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2233840 |
1 |
|
|
T22 |
86 |
|
T1 |
754 |
|
T12 |
70 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
982718 |
1 |
|
|
T22 |
16 |
|
T1 |
276 |
|
T12 |
57 |
| auto[1] |
auto[0] |
auto[1] |
141637 |
1 |
|
|
T22 |
3 |
|
T1 |
12 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
970511 |
1 |
|
|
T22 |
66 |
|
T1 |
450 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[1] |
138974 |
1 |
|
|
T22 |
1 |
|
T1 |
16 |
|
T13 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4443452 |
1 |
|
|
T22 |
177 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2210996 |
1 |
|
|
T22 |
80 |
|
T1 |
655 |
|
T12 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6376397 |
1 |
|
|
T22 |
249 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
278051 |
1 |
|
|
T22 |
8 |
|
T1 |
30 |
|
T13 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4440052 |
1 |
|
|
T22 |
127 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2214396 |
1 |
|
|
T22 |
130 |
|
T1 |
884 |
|
T12 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
980458 |
1 |
|
|
T22 |
88 |
|
T1 |
500 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
140865 |
1 |
|
|
T22 |
6 |
|
T1 |
20 |
|
T13 |
12 |
| auto[1] |
auto[1] |
auto[0] |
955887 |
1 |
|
|
T22 |
34 |
|
T1 |
354 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
137186 |
1 |
|
|
T22 |
2 |
|
T1 |
10 |
|
T13 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4442364 |
1 |
|
|
T22 |
113 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2212084 |
1 |
|
|
T22 |
144 |
|
T1 |
709 |
|
T12 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373414 |
1 |
|
|
T22 |
255 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
281034 |
1 |
|
|
T22 |
2 |
|
T1 |
39 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4419569 |
1 |
|
|
T22 |
164 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234879 |
1 |
|
|
T22 |
93 |
|
T1 |
875 |
|
T12 |
65 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
989768 |
1 |
|
|
T22 |
31 |
|
T1 |
437 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
142833 |
1 |
|
|
T1 |
21 |
|
T12 |
1 |
|
T13 |
7 |
| auto[1] |
auto[1] |
auto[0] |
964077 |
1 |
|
|
T22 |
60 |
|
T1 |
399 |
|
T12 |
24 |
| auto[1] |
auto[1] |
auto[1] |
138201 |
1 |
|
|
T22 |
2 |
|
T1 |
18 |
|
T13 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4425472 |
1 |
|
|
T22 |
190 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228976 |
1 |
|
|
T22 |
67 |
|
T1 |
836 |
|
T12 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6376929 |
1 |
|
|
T22 |
247 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
277519 |
1 |
|
|
T22 |
10 |
|
T1 |
30 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4439803 |
1 |
|
|
T22 |
97 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2214645 |
1 |
|
|
T22 |
160 |
|
T1 |
734 |
|
T12 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
971688 |
1 |
|
|
T22 |
107 |
|
T1 |
286 |
|
T12 |
19 |
| auto[1] |
auto[0] |
auto[1] |
138885 |
1 |
|
|
T22 |
5 |
|
T1 |
7 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[0] |
965438 |
1 |
|
|
T22 |
43 |
|
T1 |
418 |
|
T12 |
37 |
| auto[1] |
auto[1] |
auto[1] |
138634 |
1 |
|
|
T22 |
5 |
|
T1 |
23 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4429727 |
1 |
|
|
T22 |
153 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224721 |
1 |
|
|
T22 |
104 |
|
T1 |
865 |
|
T12 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374981 |
1 |
|
|
T22 |
248 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279467 |
1 |
|
|
T22 |
9 |
|
T1 |
41 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4432576 |
1 |
|
|
T22 |
143 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2221872 |
1 |
|
|
T22 |
114 |
|
T1 |
821 |
|
T12 |
61 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
978784 |
1 |
|
|
T22 |
57 |
|
T1 |
374 |
|
T12 |
33 |
| auto[1] |
auto[0] |
auto[1] |
140902 |
1 |
|
|
T22 |
4 |
|
T1 |
25 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
963621 |
1 |
|
|
T22 |
48 |
|
T1 |
406 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[1] |
138565 |
1 |
|
|
T22 |
5 |
|
T1 |
16 |
|
T13 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4434043 |
1 |
|
|
T22 |
152 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2220405 |
1 |
|
|
T22 |
105 |
|
T1 |
750 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374349 |
1 |
|
|
T22 |
252 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280099 |
1 |
|
|
T22 |
5 |
|
T1 |
35 |
|
T13 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4435401 |
1 |
|
|
T22 |
158 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2219047 |
1 |
|
|
T22 |
99 |
|
T1 |
824 |
|
T12 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
975021 |
1 |
|
|
T22 |
50 |
|
T1 |
410 |
|
T12 |
45 |
| auto[1] |
auto[0] |
auto[1] |
140977 |
1 |
|
|
T22 |
4 |
|
T1 |
19 |
|
T13 |
16 |
| auto[1] |
auto[1] |
auto[0] |
963927 |
1 |
|
|
T22 |
44 |
|
T1 |
379 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[1] |
139122 |
1 |
|
|
T22 |
1 |
|
T1 |
16 |
|
T13 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420376 |
1 |
|
|
T22 |
128 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234072 |
1 |
|
|
T22 |
129 |
|
T1 |
622 |
|
T12 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374083 |
1 |
|
|
T22 |
249 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280365 |
1 |
|
|
T22 |
8 |
|
T1 |
32 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430117 |
1 |
|
|
T22 |
121 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224331 |
1 |
|
|
T22 |
136 |
|
T1 |
810 |
|
T12 |
69 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
974136 |
1 |
|
|
T22 |
65 |
|
T1 |
405 |
|
T12 |
59 |
| auto[1] |
auto[0] |
auto[1] |
140592 |
1 |
|
|
T22 |
4 |
|
T1 |
14 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
969830 |
1 |
|
|
T22 |
63 |
|
T1 |
373 |
|
T12 |
9 |
| auto[1] |
auto[1] |
auto[1] |
139773 |
1 |
|
|
T22 |
4 |
|
T1 |
18 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430255 |
1 |
|
|
T22 |
89 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224193 |
1 |
|
|
T22 |
168 |
|
T1 |
567 |
|
T12 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374111 |
1 |
|
|
T22 |
254 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280337 |
1 |
|
|
T22 |
3 |
|
T1 |
25 |
|
T13 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426279 |
1 |
|
|
T22 |
142 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228169 |
1 |
|
|
T22 |
115 |
|
T1 |
553 |
|
T12 |
47 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
979944 |
1 |
|
|
T22 |
23 |
|
T1 |
263 |
|
T12 |
38 |
| auto[1] |
auto[0] |
auto[1] |
141290 |
1 |
|
|
T22 |
2 |
|
T1 |
8 |
|
T13 |
7 |
| auto[1] |
auto[1] |
auto[0] |
967888 |
1 |
|
|
T22 |
89 |
|
T1 |
265 |
|
T12 |
9 |
| auto[1] |
auto[1] |
auto[1] |
139047 |
1 |
|
|
T22 |
1 |
|
T1 |
17 |
|
T13 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4415469 |
1 |
|
|
T22 |
145 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2238979 |
1 |
|
|
T22 |
112 |
|
T1 |
794 |
|
T12 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374106 |
1 |
|
|
T22 |
247 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280342 |
1 |
|
|
T22 |
10 |
|
T1 |
34 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4427071 |
1 |
|
|
T22 |
92 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2227377 |
1 |
|
|
T22 |
165 |
|
T1 |
873 |
|
T12 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
972432 |
1 |
|
|
T22 |
89 |
|
T1 |
414 |
|
T12 |
36 |
| auto[1] |
auto[0] |
auto[1] |
139875 |
1 |
|
|
T22 |
6 |
|
T1 |
16 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
974603 |
1 |
|
|
T22 |
66 |
|
T1 |
425 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
140467 |
1 |
|
|
T22 |
4 |
|
T1 |
18 |
|
T13 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4435447 |
1 |
|
|
T22 |
105 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2219001 |
1 |
|
|
T22 |
152 |
|
T1 |
721 |
|
T12 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6372629 |
1 |
|
|
T22 |
254 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
281819 |
1 |
|
|
T22 |
3 |
|
T1 |
26 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420460 |
1 |
|
|
T22 |
155 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2233988 |
1 |
|
|
T22 |
102 |
|
T1 |
729 |
|
T12 |
52 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
977465 |
1 |
|
|
T22 |
45 |
|
T1 |
316 |
|
T12 |
31 |
| auto[1] |
auto[0] |
auto[1] |
141233 |
1 |
|
|
T22 |
1 |
|
T1 |
12 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
974704 |
1 |
|
|
T22 |
54 |
|
T1 |
387 |
|
T12 |
19 |
| auto[1] |
auto[1] |
auto[1] |
140586 |
1 |
|
|
T22 |
2 |
|
T1 |
14 |
|
T13 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4442763 |
1 |
|
|
T22 |
134 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2211685 |
1 |
|
|
T22 |
123 |
|
T1 |
739 |
|
T12 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373204 |
1 |
|
|
T22 |
254 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
281244 |
1 |
|
|
T22 |
3 |
|
T1 |
27 |
|
T13 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420405 |
1 |
|
|
T22 |
151 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234043 |
1 |
|
|
T22 |
106 |
|
T1 |
833 |
|
T12 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
983071 |
1 |
|
|
T22 |
74 |
|
T1 |
420 |
|
T12 |
29 |
| auto[1] |
auto[0] |
auto[1] |
141223 |
1 |
|
|
T22 |
2 |
|
T1 |
13 |
|
T13 |
9 |
| auto[1] |
auto[1] |
auto[0] |
969728 |
1 |
|
|
T22 |
29 |
|
T1 |
386 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
140021 |
1 |
|
|
T22 |
1 |
|
T1 |
14 |
|
T13 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4447787 |
1 |
|
|
T22 |
125 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2206661 |
1 |
|
|
T22 |
132 |
|
T1 |
875 |
|
T12 |
53 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374995 |
1 |
|
|
T22 |
252 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279453 |
1 |
|
|
T22 |
5 |
|
T1 |
17 |
|
T13 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4424450 |
1 |
|
|
T22 |
130 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2229998 |
1 |
|
|
T22 |
127 |
|
T1 |
548 |
|
T12 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
984631 |
1 |
|
|
T22 |
56 |
|
T1 |
234 |
|
T12 |
23 |
| auto[1] |
auto[0] |
auto[1] |
141119 |
1 |
|
|
T22 |
2 |
|
T1 |
8 |
|
T13 |
15 |
| auto[1] |
auto[1] |
auto[0] |
965914 |
1 |
|
|
T22 |
66 |
|
T1 |
297 |
|
T12 |
8 |
| auto[1] |
auto[1] |
auto[1] |
138334 |
1 |
|
|
T22 |
3 |
|
T1 |
9 |
|
T13 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4423082 |
1 |
|
|
T22 |
128 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2231366 |
1 |
|
|
T22 |
129 |
|
T1 |
650 |
|
T12 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373924 |
1 |
|
|
T22 |
246 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280524 |
1 |
|
|
T22 |
11 |
|
T1 |
31 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4429970 |
1 |
|
|
T22 |
102 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224478 |
1 |
|
|
T22 |
155 |
|
T1 |
805 |
|
T12 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
973248 |
1 |
|
|
T22 |
71 |
|
T1 |
472 |
|
T12 |
38 |
| auto[1] |
auto[0] |
auto[1] |
140272 |
1 |
|
|
T22 |
7 |
|
T1 |
20 |
|
T13 |
7 |
| auto[1] |
auto[1] |
auto[0] |
970706 |
1 |
|
|
T22 |
73 |
|
T1 |
302 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
140252 |
1 |
|
|
T22 |
4 |
|
T1 |
11 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420187 |
1 |
|
|
T22 |
89 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234261 |
1 |
|
|
T22 |
168 |
|
T1 |
824 |
|
T12 |
64 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374458 |
1 |
|
|
T22 |
248 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279990 |
1 |
|
|
T22 |
9 |
|
T1 |
24 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4423323 |
1 |
|
|
T22 |
86 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2231125 |
1 |
|
|
T22 |
171 |
|
T1 |
743 |
|
T12 |
72 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
981398 |
1 |
|
|
T22 |
62 |
|
T1 |
305 |
|
T12 |
38 |
| auto[1] |
auto[0] |
auto[1] |
140578 |
1 |
|
|
T22 |
2 |
|
T1 |
10 |
|
T13 |
15 |
| auto[1] |
auto[1] |
auto[0] |
969737 |
1 |
|
|
T22 |
100 |
|
T1 |
414 |
|
T12 |
32 |
| auto[1] |
auto[1] |
auto[1] |
139412 |
1 |
|
|
T22 |
7 |
|
T1 |
14 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426099 |
1 |
|
|
T22 |
133 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228349 |
1 |
|
|
T22 |
124 |
|
T1 |
678 |
|
T12 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6373816 |
1 |
|
|
T22 |
251 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280632 |
1 |
|
|
T22 |
6 |
|
T1 |
28 |
|
T13 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4423119 |
1 |
|
|
T22 |
162 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2231329 |
1 |
|
|
T22 |
95 |
|
T1 |
658 |
|
T12 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
986563 |
1 |
|
|
T22 |
36 |
|
T1 |
367 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
142198 |
1 |
|
|
T22 |
5 |
|
T1 |
16 |
|
T13 |
8 |
| auto[1] |
auto[1] |
auto[0] |
964134 |
1 |
|
|
T22 |
53 |
|
T1 |
263 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[1] |
138434 |
1 |
|
|
T22 |
1 |
|
T1 |
12 |
|
T13 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430896 |
1 |
|
|
T22 |
94 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2223552 |
1 |
|
|
T22 |
163 |
|
T1 |
576 |
|
T12 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6376195 |
1 |
|
|
T22 |
249 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
278253 |
1 |
|
|
T22 |
8 |
|
T1 |
37 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4439901 |
1 |
|
|
T22 |
96 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2214547 |
1 |
|
|
T22 |
161 |
|
T1 |
782 |
|
T12 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
970437 |
1 |
|
|
T22 |
59 |
|
T1 |
452 |
|
T12 |
28 |
| auto[1] |
auto[0] |
auto[1] |
139303 |
1 |
|
|
T22 |
3 |
|
T1 |
22 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
965857 |
1 |
|
|
T22 |
94 |
|
T1 |
293 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[1] |
138950 |
1 |
|
|
T22 |
5 |
|
T1 |
15 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426928 |
1 |
|
|
T22 |
155 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2227520 |
1 |
|
|
T22 |
102 |
|
T1 |
845 |
|
T12 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374913 |
1 |
|
|
T22 |
251 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279535 |
1 |
|
|
T22 |
6 |
|
T1 |
28 |
|
T13 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4428875 |
1 |
|
|
T22 |
136 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2225573 |
1 |
|
|
T22 |
121 |
|
T1 |
679 |
|
T12 |
62 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
978841 |
1 |
|
|
T22 |
83 |
|
T1 |
283 |
|
T12 |
47 |
| auto[1] |
auto[0] |
auto[1] |
140533 |
1 |
|
|
T22 |
6 |
|
T1 |
8 |
|
T13 |
11 |
| auto[1] |
auto[1] |
auto[0] |
967197 |
1 |
|
|
T22 |
32 |
|
T1 |
368 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
139002 |
1 |
|
|
T1 |
20 |
|
T13 |
12 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4439252 |
1 |
|
|
T22 |
151 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2215196 |
1 |
|
|
T22 |
106 |
|
T1 |
689 |
|
T12 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6372826 |
1 |
|
|
T22 |
250 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
281622 |
1 |
|
|
T22 |
7 |
|
T1 |
29 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420933 |
1 |
|
|
T22 |
120 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2233515 |
1 |
|
|
T22 |
137 |
|
T1 |
845 |
|
T12 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
985462 |
1 |
|
|
T22 |
98 |
|
T1 |
417 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
143000 |
1 |
|
|
T22 |
6 |
|
T1 |
11 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
966431 |
1 |
|
|
T22 |
32 |
|
T1 |
399 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
138622 |
1 |
|
|
T22 |
1 |
|
T1 |
18 |
|
T12 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420626 |
1 |
|
|
T22 |
109 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2233822 |
1 |
|
|
T22 |
148 |
|
T1 |
859 |
|
T12 |
49 |