Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4431333 |
1 |
|
|
T22 |
99 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2223115 |
1 |
|
|
T22 |
158 |
|
T1 |
865 |
|
T12 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6375140 |
1 |
|
|
T22 |
252 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279308 |
1 |
|
|
T22 |
5 |
|
T1 |
23 |
|
T13 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4432131 |
1 |
|
|
T22 |
140 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2222317 |
1 |
|
|
T22 |
117 |
|
T1 |
642 |
|
T12 |
58 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
978494 |
1 |
|
|
T22 |
51 |
|
T1 |
221 |
|
T12 |
40 |
| auto[1] |
auto[0] |
auto[1] |
140512 |
1 |
|
|
T22 |
2 |
|
T1 |
6 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[0] |
964515 |
1 |
|
|
T22 |
61 |
|
T1 |
398 |
|
T12 |
18 |
| auto[1] |
auto[1] |
auto[1] |
138796 |
1 |
|
|
T22 |
3 |
|
T1 |
17 |
|
T13 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |