Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4428224 |
1 |
|
|
T22 |
113 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2226224 |
1 |
|
|
T22 |
144 |
|
T1 |
696 |
|
T12 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6372233 |
1 |
|
|
T22 |
248 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
282215 |
1 |
|
|
T22 |
9 |
|
T1 |
28 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4414945 |
1 |
|
|
T22 |
132 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2239503 |
1 |
|
|
T22 |
125 |
|
T1 |
801 |
|
T12 |
81 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
981312 |
1 |
|
|
T22 |
48 |
|
T1 |
389 |
|
T12 |
46 |
| auto[1] |
auto[0] |
auto[1] |
140781 |
1 |
|
|
T22 |
7 |
|
T1 |
14 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
975976 |
1 |
|
|
T22 |
68 |
|
T1 |
384 |
|
T12 |
34 |
| auto[1] |
auto[1] |
auto[1] |
141434 |
1 |
|
|
T22 |
2 |
|
T1 |
14 |
|
T13 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |