Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4436975 |
1 |
|
|
T22 |
90 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2217473 |
1 |
|
|
T22 |
167 |
|
T1 |
736 |
|
T12 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6372279 |
1 |
|
|
T22 |
253 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
282169 |
1 |
|
|
T22 |
4 |
|
T1 |
22 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4419248 |
1 |
|
|
T22 |
140 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2235200 |
1 |
|
|
T22 |
117 |
|
T1 |
671 |
|
T12 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
984089 |
1 |
|
|
T22 |
55 |
|
T1 |
348 |
|
T12 |
27 |
| auto[1] |
auto[0] |
auto[1] |
142517 |
1 |
|
|
T22 |
1 |
|
T1 |
12 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
968942 |
1 |
|
|
T22 |
58 |
|
T1 |
301 |
|
T12 |
9 |
| auto[1] |
auto[1] |
auto[1] |
139652 |
1 |
|
|
T22 |
3 |
|
T1 |
10 |
|
T13 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |