Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4424920 |
1 |
|
|
T22 |
139 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2229528 |
1 |
|
|
T22 |
118 |
|
T1 |
740 |
|
T12 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374210 |
1 |
|
|
T22 |
249 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280238 |
1 |
|
|
T22 |
8 |
|
T1 |
34 |
|
T13 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4429987 |
1 |
|
|
T22 |
122 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224461 |
1 |
|
|
T22 |
135 |
|
T1 |
1033 |
|
T12 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
978162 |
1 |
|
|
T22 |
80 |
|
T1 |
582 |
|
T12 |
21 |
| auto[1] |
auto[0] |
auto[1] |
140660 |
1 |
|
|
T22 |
5 |
|
T1 |
21 |
|
T13 |
16 |
| auto[1] |
auto[1] |
auto[0] |
966061 |
1 |
|
|
T22 |
47 |
|
T1 |
417 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
139578 |
1 |
|
|
T22 |
3 |
|
T1 |
13 |
|
T13 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |