Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4438698 |
1 |
|
|
T22 |
150 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2215750 |
1 |
|
|
T22 |
107 |
|
T1 |
630 |
|
T12 |
54 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6374138 |
1 |
|
|
T22 |
251 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
280310 |
1 |
|
|
T22 |
6 |
|
T1 |
42 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4428809 |
1 |
|
|
T22 |
132 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2225639 |
1 |
|
|
T22 |
125 |
|
T1 |
916 |
|
T12 |
63 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
979782 |
1 |
|
|
T22 |
69 |
|
T1 |
487 |
|
T12 |
38 |
| auto[1] |
auto[0] |
auto[1] |
141800 |
1 |
|
|
T22 |
4 |
|
T1 |
20 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
965547 |
1 |
|
|
T22 |
50 |
|
T1 |
387 |
|
T12 |
24 |
| auto[1] |
auto[1] |
auto[1] |
138510 |
1 |
|
|
T22 |
2 |
|
T1 |
22 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |