Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4411865 |
1 |
|
|
T22 |
109 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2242583 |
1 |
|
|
T22 |
148 |
|
T1 |
874 |
|
T12 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5643683 |
1 |
|
|
T22 |
172 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1010765 |
1 |
|
|
T22 |
85 |
|
T1 |
171 |
|
T12 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4423468 |
1 |
|
|
T22 |
75 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2230980 |
1 |
|
|
T22 |
182 |
|
T1 |
808 |
|
T12 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
602126 |
1 |
|
|
T22 |
37 |
|
T1 |
251 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
500375 |
1 |
|
|
T22 |
45 |
|
T1 |
98 |
|
T12 |
19 |
| auto[1] |
auto[1] |
auto[0] |
618089 |
1 |
|
|
T22 |
60 |
|
T1 |
386 |
|
T13 |
263 |
| auto[1] |
auto[1] |
auto[1] |
510390 |
1 |
|
|
T22 |
40 |
|
T1 |
73 |
|
T12 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |