Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4431731 |
1 |
|
|
T22 |
113 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2222717 |
1 |
|
|
T22 |
144 |
|
T1 |
879 |
|
T12 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5650724 |
1 |
|
|
T22 |
142 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1003724 |
1 |
|
|
T22 |
115 |
|
T1 |
209 |
|
T12 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4435241 |
1 |
|
|
T22 |
104 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2219207 |
1 |
|
|
T22 |
153 |
|
T1 |
722 |
|
T12 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
609944 |
1 |
|
|
T22 |
23 |
|
T1 |
193 |
|
T12 |
7 |
| auto[1] |
auto[0] |
auto[1] |
503861 |
1 |
|
|
T22 |
47 |
|
T1 |
85 |
|
T12 |
17 |
| auto[1] |
auto[1] |
auto[0] |
605539 |
1 |
|
|
T22 |
15 |
|
T1 |
320 |
|
T13 |
230 |
| auto[1] |
auto[1] |
auto[1] |
499863 |
1 |
|
|
T22 |
68 |
|
T1 |
124 |
|
T12 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |