Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4443452 |
1 |
|
|
T22 |
177 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2210996 |
1 |
|
|
T22 |
80 |
|
T1 |
655 |
|
T12 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5643315 |
1 |
|
|
T22 |
185 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1011133 |
1 |
|
|
T22 |
72 |
|
T1 |
108 |
|
T12 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4421107 |
1 |
|
|
T22 |
155 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2233341 |
1 |
|
|
T22 |
102 |
|
T1 |
814 |
|
T12 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
617080 |
1 |
|
|
T22 |
18 |
|
T1 |
383 |
|
T12 |
14 |
| auto[1] |
auto[0] |
auto[1] |
513774 |
1 |
|
|
T22 |
49 |
|
T1 |
79 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[0] |
605128 |
1 |
|
|
T22 |
12 |
|
T1 |
323 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[1] |
497359 |
1 |
|
|
T22 |
23 |
|
T1 |
29 |
|
T12 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |