Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4442364 |
1 |
|
|
T22 |
113 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2212084 |
1 |
|
|
T22 |
144 |
|
T1 |
709 |
|
T12 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5641192 |
1 |
|
|
T22 |
210 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1013256 |
1 |
|
|
T22 |
47 |
|
T1 |
178 |
|
T12 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4413829 |
1 |
|
|
T22 |
126 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2240619 |
1 |
|
|
T22 |
131 |
|
T1 |
814 |
|
T12 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
627150 |
1 |
|
|
T22 |
36 |
|
T1 |
352 |
|
T13 |
158 |
| auto[1] |
auto[0] |
auto[1] |
514050 |
1 |
|
|
T22 |
13 |
|
T1 |
92 |
|
T13 |
26 |
| auto[1] |
auto[1] |
auto[0] |
600213 |
1 |
|
|
T22 |
48 |
|
T1 |
284 |
|
T13 |
267 |
| auto[1] |
auto[1] |
auto[1] |
499206 |
1 |
|
|
T22 |
34 |
|
T1 |
86 |
|
T12 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |