Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4425472 |
1 |
|
|
T22 |
190 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228976 |
1 |
|
|
T22 |
67 |
|
T1 |
836 |
|
T12 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5643334 |
1 |
|
|
T22 |
209 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1011114 |
1 |
|
|
T22 |
48 |
|
T1 |
183 |
|
T12 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4418230 |
1 |
|
|
T22 |
117 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2236218 |
1 |
|
|
T22 |
140 |
|
T1 |
825 |
|
T12 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
613937 |
1 |
|
|
T22 |
70 |
|
T1 |
278 |
|
T12 |
14 |
| auto[1] |
auto[0] |
auto[1] |
509540 |
1 |
|
|
T22 |
34 |
|
T1 |
64 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[0] |
611167 |
1 |
|
|
T22 |
22 |
|
T1 |
364 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
501574 |
1 |
|
|
T22 |
14 |
|
T1 |
119 |
|
T13 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |