Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6375433 |
1 |
|
|
T22 |
250 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
279015 |
1 |
|
|
T22 |
7 |
|
T1 |
28 |
|
T13 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4438282 |
1 |
|
|
T22 |
129 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2216166 |
1 |
|
|
T22 |
128 |
|
T1 |
673 |
|
T12 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
969467 |
1 |
|
|
T22 |
65 |
|
T1 |
262 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
138962 |
1 |
|
|
T22 |
3 |
|
T1 |
14 |
|
T13 |
8 |
| auto[1] |
auto[1] |
auto[0] |
967684 |
1 |
|
|
T22 |
56 |
|
T1 |
383 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
140053 |
1 |
|
|
T22 |
4 |
|
T1 |
14 |
|
T13 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |