Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4429727 |
1 |
|
|
T22 |
153 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224721 |
1 |
|
|
T22 |
104 |
|
T1 |
865 |
|
T12 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5654486 |
1 |
|
|
T22 |
194 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
999962 |
1 |
|
|
T22 |
63 |
|
T1 |
142 |
|
T12 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4433901 |
1 |
|
|
T22 |
140 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2220547 |
1 |
|
|
T22 |
117 |
|
T1 |
643 |
|
T12 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
608400 |
1 |
|
|
T22 |
37 |
|
T1 |
242 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
500035 |
1 |
|
|
T22 |
44 |
|
T1 |
47 |
|
T12 |
16 |
| auto[1] |
auto[1] |
auto[0] |
612185 |
1 |
|
|
T22 |
17 |
|
T1 |
259 |
|
T13 |
171 |
| auto[1] |
auto[1] |
auto[1] |
499927 |
1 |
|
|
T22 |
19 |
|
T1 |
95 |
|
T12 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |