Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4434043 |
1 |
|
|
T22 |
152 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2220405 |
1 |
|
|
T22 |
105 |
|
T1 |
750 |
|
T12 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5641825 |
1 |
|
|
T22 |
177 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1012623 |
1 |
|
|
T22 |
80 |
|
T1 |
236 |
|
T12 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4419767 |
1 |
|
|
T22 |
126 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234681 |
1 |
|
|
T22 |
131 |
|
T1 |
863 |
|
T12 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
617161 |
1 |
|
|
T22 |
18 |
|
T1 |
345 |
|
T12 |
12 |
| auto[1] |
auto[0] |
auto[1] |
511362 |
1 |
|
|
T22 |
53 |
|
T1 |
119 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[0] |
604897 |
1 |
|
|
T22 |
33 |
|
T1 |
282 |
|
T13 |
271 |
| auto[1] |
auto[1] |
auto[1] |
501261 |
1 |
|
|
T22 |
27 |
|
T1 |
117 |
|
T12 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |