Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4420376 |
1 |
|
|
T22 |
128 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2234072 |
1 |
|
|
T22 |
129 |
|
T1 |
622 |
|
T12 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5645252 |
1 |
|
|
T22 |
217 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1009196 |
1 |
|
|
T22 |
40 |
|
T1 |
193 |
|
T12 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4423282 |
1 |
|
|
T22 |
140 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2231166 |
1 |
|
|
T22 |
117 |
|
T1 |
836 |
|
T12 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
615772 |
1 |
|
|
T22 |
26 |
|
T1 |
330 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
507257 |
1 |
|
|
T22 |
24 |
|
T1 |
78 |
|
T12 |
14 |
| auto[1] |
auto[1] |
auto[0] |
606198 |
1 |
|
|
T22 |
51 |
|
T1 |
313 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
501939 |
1 |
|
|
T22 |
16 |
|
T1 |
115 |
|
T12 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |