Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4430255 |
1 |
|
|
T22 |
89 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2224193 |
1 |
|
|
T22 |
168 |
|
T1 |
567 |
|
T12 |
17 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5651941 |
1 |
|
|
T22 |
180 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1002507 |
1 |
|
|
T22 |
77 |
|
T1 |
239 |
|
T12 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426564 |
1 |
|
|
T22 |
55 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2227884 |
1 |
|
|
T22 |
202 |
|
T1 |
775 |
|
T12 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
617412 |
1 |
|
|
T22 |
48 |
|
T1 |
284 |
|
T13 |
183 |
| auto[1] |
auto[0] |
auto[1] |
504159 |
1 |
|
|
T22 |
37 |
|
T1 |
152 |
|
T12 |
18 |
| auto[1] |
auto[1] |
auto[0] |
607965 |
1 |
|
|
T22 |
77 |
|
T1 |
252 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
498348 |
1 |
|
|
T22 |
40 |
|
T1 |
87 |
|
T12 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |