Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4415469 |
1 |
|
|
T22 |
145 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2238979 |
1 |
|
|
T22 |
112 |
|
T1 |
794 |
|
T12 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5649216 |
1 |
|
|
T22 |
202 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1005232 |
1 |
|
|
T22 |
55 |
|
T1 |
260 |
|
T12 |
35 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4426246 |
1 |
|
|
T22 |
118 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2228202 |
1 |
|
|
T22 |
139 |
|
T1 |
821 |
|
T12 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
608036 |
1 |
|
|
T22 |
60 |
|
T1 |
275 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
495407 |
1 |
|
|
T22 |
38 |
|
T1 |
104 |
|
T12 |
22 |
| auto[1] |
auto[1] |
auto[0] |
614934 |
1 |
|
|
T22 |
24 |
|
T1 |
286 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
509825 |
1 |
|
|
T22 |
17 |
|
T1 |
156 |
|
T12 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |