Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4435447 |
1 |
|
|
T22 |
105 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2219001 |
1 |
|
|
T22 |
152 |
|
T1 |
721 |
|
T12 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5652071 |
1 |
|
|
T22 |
212 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1002377 |
1 |
|
|
T22 |
45 |
|
T1 |
177 |
|
T13 |
112 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4443753 |
1 |
|
|
T22 |
169 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2210695 |
1 |
|
|
T22 |
88 |
|
T1 |
791 |
|
T12 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
608207 |
1 |
|
|
T22 |
28 |
|
T1 |
333 |
|
T12 |
19 |
| auto[1] |
auto[0] |
auto[1] |
502261 |
1 |
|
|
T22 |
9 |
|
T1 |
85 |
|
T13 |
59 |
| auto[1] |
auto[1] |
auto[0] |
600111 |
1 |
|
|
T22 |
15 |
|
T1 |
281 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
500116 |
1 |
|
|
T22 |
36 |
|
T1 |
92 |
|
T13 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |