Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4442763 |
1 |
|
|
T22 |
134 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2211685 |
1 |
|
|
T22 |
123 |
|
T1 |
739 |
|
T12 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5651992 |
1 |
|
|
T22 |
214 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1002456 |
1 |
|
|
T22 |
43 |
|
T1 |
139 |
|
T12 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4438302 |
1 |
|
|
T22 |
185 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2216146 |
1 |
|
|
T22 |
72 |
|
T1 |
790 |
|
T12 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
614284 |
1 |
|
|
T22 |
15 |
|
T1 |
348 |
|
T12 |
15 |
| auto[1] |
auto[0] |
auto[1] |
506495 |
1 |
|
|
T22 |
23 |
|
T1 |
94 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
599406 |
1 |
|
|
T22 |
14 |
|
T1 |
303 |
|
T12 |
13 |
| auto[1] |
auto[1] |
auto[1] |
495961 |
1 |
|
|
T22 |
20 |
|
T1 |
45 |
|
T12 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |