Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4447787 |
1 |
|
|
T22 |
125 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2206661 |
1 |
|
|
T22 |
132 |
|
T1 |
875 |
|
T12 |
53 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5649336 |
1 |
|
|
T22 |
191 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
1005112 |
1 |
|
|
T22 |
66 |
|
T1 |
192 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4438019 |
1 |
|
|
T22 |
132 |
|
T23 |
314 |
|
T24 |
227 |
| auto[1] |
2216429 |
1 |
|
|
T22 |
125 |
|
T1 |
827 |
|
T12 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
612148 |
1 |
|
|
T22 |
32 |
|
T1 |
208 |
|
T12 |
15 |
| auto[1] |
auto[0] |
auto[1] |
507897 |
1 |
|
|
T22 |
28 |
|
T1 |
98 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
599169 |
1 |
|
|
T22 |
27 |
|
T1 |
427 |
|
T12 |
14 |
| auto[1] |
auto[1] |
auto[1] |
497215 |
1 |
|
|
T22 |
38 |
|
T1 |
94 |
|
T13 |
67 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |